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| version 1.49, 2004/02/29 03:10:02 | version 1.53, 2004/03/04 17:36:05 |
|---|---|
| Line 108 static void bios_reinitbyswitch(void) { | Line 108 static void bios_reinitbyswitch(void) { |
| } | } |
| mem[MEMB_F2DD_MODE] = 0xff; | mem[MEMB_F2DD_MODE] = 0xff; |
| #if defined(SUPPORT_31KHZ) | #if defined(SUPPORT_CRT31KHZ) |
| mem[MEMB_CRT_BIOS] = 0x80; | mem[MEMB_CRT_BIOS] = 0x80; |
| #endif | #endif |
| #if defined(SUPPORT_PC9821) | #if defined(SUPPORT_PC9821) |
| Line 275 static void bios_boot(void) { | Line 275 static void bios_boot(void) { |
| // TRACEOUT(("CPU Reset... SS:SP = %.4x:%.4x", CPU_SS, CPU_SP)); | // TRACEOUT(("CPU Reset... SS:SP = %.4x:%.4x", CPU_SS, CPU_SP)); |
| } | } |
| else { | else { |
| bios_memclear(); | // bios_memclear(); |
| bios_vectorset(); | bios_vectorset(); |
| bios0x09_init(); | bios0x09_init(); |
| bios_reinitbyswitch(); | bios_reinitbyswitch(); |
| Line 307 static void bios0x1f(void) { | Line 307 static void bios0x1f(void) { |
| UINT l; | UINT l; |
| if (CPU_AH == 0x90) { | if (CPU_AH == 0x90) { |
| i286_memstr_read(CPU_ES, CPU_BX + 0x10, work, 0x10); | MEML_READSTR(CPU_ES, CPU_BX + 0x10, work, 0x10); |
| src = work[2] + (work[3] << 8) + (work[4] << 16) + CPU_SI; | src = work[2] + (work[3] << 8) + (work[4] << 16) + CPU_SI; |
| dst = work[10] + (work[11] << 8) + (work[12] << 16) + CPU_DI; | dst = work[10] + (work[11] << 8) + (work[12] << 16) + CPU_DI; |
| leng = LOW16(CPU_CX - 1) + 1; | leng = LOW16(CPU_CX - 1) + 1; |
| Line 322 static void bios0x1f(void) { | Line 322 static void bios0x1f(void) { |
| TRACEOUT(("src:%08x dst:%08x leng:%08x", src, dst, leng)); | TRACEOUT(("src:%08x dst:%08x leng:%08x", src, dst, leng)); |
| do { | do { |
| l = min(leng, 256); | l = min(leng, 256); |
| i286_memx_read(src, work, l); | MEML_READ(src, work, l); |
| i286_memx_write(dst, work, l); | MEML_WRITE(dst, work, l); |
| src += l; | src += l; |
| dst += l; | dst += l; |
| leng -= l; | leng -= l; |