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| version 1.1.1.1, 2003/10/16 17:58:20 | version 1.7, 2011/01/15 18:04:42 |
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| Line 1 | Line 1 |
| #include "compiler.h" | #include "compiler.h" |
| #include "i286.h" | #include "cpucore.h" |
| #include "memory.h" | |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| #include "bios.h" | #include "bios.h" |
| #include "biosmem.h" | |
| #define baseport 0x00c8 | #define baseport 0x00c8 |
| void bios0x12(void) { | void bios0x12(void) { |
| BYTE stat; | UINT8 status; |
| BYTE result; | UINT8 result; |
| BYTE *p; | UINT8 *p; |
| BYTE drv; | UINT8 drv; |
| UINT8 drvbit; | |
| // TRACE_("BIOS", 0x12); | // TRACE_("BIOS", 0x12); |
| iocore_out8(0x08, 0x20); | iocore_out8(0x08, 0x20); |
| Line 21 void bios0x12(void) { | Line 22 void bios0x12(void) { |
| iocore_out8(0x00, 0x20); | iocore_out8(0x00, 0x20); |
| } | } |
| stat = iocore_inp8(baseport); | status = iocore_inp8(baseport); |
| while(1) { | while(1) { |
| if (!(stat & FDCSTAT_CB)) { | if (!(status & FDCSTAT_CB)) { |
| if ((stat & (FDCSTAT_RQM | FDCSTAT_DIO)) != FDCSTAT_RQM) { | if ((status & (FDCSTAT_RQM | FDCSTAT_DIO)) != FDCSTAT_RQM) { |
| break; | break; |
| } | } |
| iocore_out8(baseport+2, 0x08); | iocore_out8(baseport+2, 0x08); |
| stat = iocore_inp8(baseport); | status = iocore_inp8(baseport); |
| } | } |
| if ((stat & (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) | if ((status & (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) |
| != (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) { | != (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) { |
| break; | break; |
| } | } |
| Line 42 void bios0x12(void) { | Line 43 void bios0x12(void) { |
| break; | break; |
| } | } |
| drv = result & 3; | drv = result & 3; |
| drvbit = 0x10 << drv; | |
| if (result & (FDCRLT_IC1 | FDCRLT_SE)) { | if (result & (FDCRLT_IC1 | FDCRLT_SE)) { |
| p = mem + 0x005d8 + (drv * 2); | p = mem + 0x005d8 + (drv * 2); |
| } | } |
| Line 50 void bios0x12(void) { | Line 52 void bios0x12(void) { |
| } | } |
| while(1) { | while(1) { |
| *p++ = result; | *p++ = result; |
| stat = iocore_inp8(baseport); | status = iocore_inp8(baseport); |
| if ((stat & (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) | if ((status & (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) |
| != (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) { | != (FDCSTAT_RQM | FDCSTAT_DIO | FDCSTAT_CB)) { |
| break; | break; |
| } | } |
| result = iocore_inp8(baseport+2); | result = iocore_inp8(baseport+2); |
| } | } |
| mem[0x0055f] |= drvbit; | |
| } | } |
| } | } |