| version 1.17, 2004/02/14 07:56:51 | version 1.28, 2004/02/29 07:36:56 | 
| Line 2 | Line 2 | 
 | #include        "cpucore.h" | #include        "cpucore.h" | 
 | #include        "pccore.h" | #include        "pccore.h" | 
 | #include        "iocore.h" | #include        "iocore.h" | 
 |  | #include        "gdc_sub.h" | 
 | #include        "bios.h" | #include        "bios.h" | 
 | #include        "biosmem.h" | #include        "biosmem.h" | 
 | #include        "font.h" | #include        "font.h" | 
| Line 37  typedef struct { | Line 38  typedef struct { | 
 | UINT8   cl; | UINT8   cl; | 
 | } CRTDATA; | } CRTDATA; | 
 |  |  | 
| static const CRTDATA crtdata[4] = { | static const UINT8 modenum[4] = {3, 1, 0, 2}; | 
| {0x07,  0x00, 0x07, 0x08}, |  | 
| {0x09,  0x1f, 0x08, 0x08}, | static const CRTDATA crtdata[7] = { | 
| {0x0f,  0x00, 0x0f, 0x10}, | {0x07,  0x00, 0x07, 0x08},              // 200-20 | 
| {0x13,  0x1e, 0x11, 0x10}}; | {0x09,  0x1f, 0x08, 0x08},              // 200-25 | 
|  | {0x0f,  0x00, 0x0f, 0x10},              // 400-20 | 
|  | {0x13,  0x1e, 0x11, 0x10},              // 400-25 | 
|  | {0x17,  0x1c, 0x13, 0x10},              // 480-20 | 
|  | {0x12,  0x1f, 0x11, 0x10},              // 480-25 | 
|  | {0x0f,  0x00, 0x0f, 0x10}};             // 480-30 | 
|  |  | 
|  | static const UINT8 gdcmastersync[6][8] = { | 
|  | {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94},              // 15 | 
|  | {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65},              // 24 | 
|  | {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89},              // 31 | 
|  | {0x10,0x4e,0x4b,0x0c,0x03,0x06,0xe0,0x95},              // 31-480:20 | 
|  | {0x10,0x4e,0x4b,0x0c,0x03,0x0b,0xdb,0x95},              // 31-480:25 | 
|  | {0x10,0x4e,0x4b,0x0c,0x03,0x06,0xe0,0x95}};             // 31-480:30 | 
|  |  | 
|  | static const UINT8 gdcslavesync[6][8] = { | 
|  | {0x02,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94},              // 15-L | 
|  | {0x02,0x4e,0x4b,0x0c,0x83,0x06,0xe0,0x95},              // 31-H | 
|  | {0x02,0x26,0x03,0x11,0x83,0x07,0x90,0x65},              // 24-L | 
|  | {0x02,0x4e,0x07,0x25,0x87,0x07,0x90,0x65},              // 24-M | 
|  | {0x02,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89},              // 31-L | 
|  | {0x02,0x4e,0x47,0x0c,0x87,0x0d,0x90,0x89}};             // 31-M | 
 |  |  | 
 | typedef struct { | typedef struct { | 
 | UINT8   lr; | UINT8   lr; | 
| Line 75  static UINT16 keyget(void) { | Line 97  static UINT16 keyget(void) { | 
 | return(0xffff); | return(0xffff); | 
 | } | } | 
 |  |  | 
| static void bios0x18_10(REG8 curdel) { |  | 
|  | // ---- master | 
|  |  | 
|  | void bios0x18_0a(REG8 mode) { | 
|  |  | 
|  | const CRTDATA   *crt; | 
|  |  | 
|  | gdc_forceready(GDCWORK_MASTER); | 
|  |  | 
|  | gdc.mode1 &= ~(0x2d); | 
|  | mem[MEMB_CRT_STS_FLAG] = mode; | 
|  | crt = crtdata; | 
|  | if (!(np2cfg.dipsw[0] & 1)) { | 
|  | mem[MEMB_CRT_STS_FLAG] |= 0x80; | 
|  | gdc.mode1 |= 0x08; | 
|  | crt += 2; | 
|  | } | 
|  | if (mode & 0x01) { | 
|  | crt += 1;                                               // 20行 | 
|  | } | 
|  | if (mode & 0x02) { | 
|  | gdc.mode1 |= 0x04;                              // 40桁 | 
|  | } | 
|  | if (mode & 0x04) { | 
|  | gdc.mode1 |= 0x01;                              // アトリビュート | 
|  | } | 
|  | if (mode & 0x08) { | 
|  | gdc.mode1 |= 0x20;                              // コードアクセス | 
|  | } | 
|  | mem[MEMB_CRT_RASTER] = crt->raster; | 
|  | crtc.reg.pl = crt->pl; | 
|  | crtc.reg.bl = crt->bl; | 
|  | crtc.reg.cl = crt->cl; | 
|  | crtc.reg.ssl = 0; | 
|  | gdc_restorekacmode(); | 
|  | bios0x18_10(0); | 
|  | } | 
|  |  | 
|  | static void bios0x18_0f(UINT seg, UINT off, REG8 num, REG8 cnt) { | 
|  |  | 
|  | BYTE    *p; | 
|  | UINT    raster; | 
|  | UINT    t; | 
|  |  | 
|  | SETBIOSMEM16(0x0053e, (UINT16)off); | 
|  | SETBIOSMEM16(0x00540, (UINT16)seg); | 
|  | mem[0x00547] = num; | 
|  | mem[0x0053D] = cnt; | 
|  | p = gdc.m.para + GDC_SCROLL + (num << 2); | 
|  |  | 
|  | #if defined(SUPPORT_CRT31KHZ) | 
|  | if (mem[MEMB_CRT_BIOS] & 0x80) { | 
|  | raster = (mem[MEMB_CRT_RASTER] + 1) << 4; | 
|  | } | 
|  | else { | 
|  | #endif | 
|  | if (!(mem[MEMB_CRT_STS_FLAG] & 0x01)) {         // 25 | 
|  | raster = 8 << 4; | 
|  | } | 
|  | else {                                                                          // 20 | 
|  | raster = 16 << 4; | 
|  | } | 
|  | if (mem[MEMB_CRT_STS_FLAG] & 0x80) { | 
|  | raster <<= 1; | 
|  | } | 
|  | #if defined(SUPPORT_CRT31KHZ) | 
|  | } | 
|  | #endif | 
|  |  | 
|  | while((cnt--) && (p < (gdc.m.para + GDC_SCROLL + 0x10))) { | 
|  | t = i286_memword_read(seg, off); | 
|  | t >>= 1; | 
|  | STOREINTELWORD(p, t); | 
|  | t = i286_memword_read(seg, off + 2); | 
|  | t *= raster; | 
|  | STOREINTELWORD(p + 2, t); | 
|  | off += 4; | 
|  | p += 4; | 
|  | } | 
|  | gdcs.textdisp |= GDCSCRN_ALLDRAW2; | 
|  | screenupdate |= 2; | 
|  | } | 
|  |  | 
|  | void bios0x18_10(REG8 curdel) { | 
 |  |  | 
 | UINT8   sts; | UINT8   sts; | 
 | UINT    pos; | UINT    pos; | 
| Line 93  static void bios0x18_10(REG8 curdel) { | Line 198  static void bios0x18_10(REG8 curdel) { | 
 | gdcs.textdisp |= GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | 
 | } | } | 
 |  |  | 
| void bios0x18_16(BYTE chr, BYTE atr) { | REG16 bios0x18_14(REG16 seg, REG16 off, REG16 code) { | 
|  |  | 
|  | UINT16  size; | 
|  | const BYTE      *p; | 
|  | BYTE    buf[32]; | 
|  | UINT    i; | 
|  |  | 
|  | switch(code >> 8) { | 
|  | case 0x00:                      // 8x8 | 
|  | size = 0x0101; | 
|  | i286_memword_write(seg, off, 0x0101); | 
|  | p = fontrom + 0x82000 + ((code & 0xff) << 4); | 
|  | i286_memstr_write(seg, off + 2, p, 8); | 
|  | break; | 
|  |  | 
|  | case 0x28:                      // 8x16 KANJI | 
|  | case 0x29: | 
|  | case 0x2a: | 
|  | case 0x2b: | 
|  | size = 0x0102; | 
|  | i286_memword_write(seg, off, 0x0102); | 
|  | p = fontrom; | 
|  | p += (code & 0x7f) << 12; | 
|  | p += (((code >> 8) - 0x20) & 0x7f) << 4; | 
|  | i286_memstr_write(seg, off + 2, p, 16); | 
|  | break; | 
|  |  | 
|  | case 0x80:                      // 8x16 ANK | 
|  | size = 0x0102; | 
|  | p = fontrom + 0x80000 + ((code & 0xff) << 4); | 
|  | i286_memstr_write(seg, off + 2, p, 16); | 
|  | break; | 
|  |  | 
|  | default: | 
|  | size = 0x0202; | 
|  | p = fontrom; | 
|  | p += (code & 0x7f) << 12; | 
|  | p += (((code >> 8) - 0x20) & 0x7f) << 4; | 
|  | for (i=0; i<16; i++, p++) { | 
|  | buf[i*2+0] = *p; | 
|  | buf[i*2+1] = *(p+0x800); | 
|  | } | 
|  | i286_memstr_write(seg, off + 2, buf, 32); | 
|  | break; | 
|  | } | 
|  | i286_memword_write(seg, off, size); | 
|  | return(size); | 
|  | } | 
|  |  | 
|  | static void bios0x18_1a(REG16 seg, REG16 off, REG16 code) { | 
|  |  | 
|  | BYTE    *p; | 
|  | BYTE    buf[32]; | 
|  | UINT    i; | 
|  |  | 
|  | if (((code >> 8) & 0x7e) == 0x76) { | 
|  | i286_memstr_read(seg, off + 2, buf, 32); | 
|  | p = fontrom; | 
|  | p += (code & 0x7f) << 12; | 
|  | p += (((code >> 8) - 0x20) & 0x7f) << 4; | 
|  | for (i=0; i<16; i++, p++) { | 
|  | *p = buf[i*2+0]; | 
|  | *(p+0x800) = buf[i*2+1]; | 
|  | } | 
|  | cgwindow.writable |= 0x80; | 
|  | } | 
|  | } | 
|  |  | 
|  | void bios0x18_16(REG8 chr, REG8 atr) { | 
 |  |  | 
 | UINT32  i; | UINT32  i; | 
 |  |  | 
| Line 107  void bios0x18_16(BYTE chr, BYTE atr) { | Line 280  void bios0x18_16(BYTE chr, BYTE atr) { | 
 | gdcs.textdisp |= GDCSCRN_ALLDRAW; | gdcs.textdisp |= GDCSCRN_ALLDRAW; | 
 | } | } | 
 |  |  | 
 | #define SWAPU16(a, b) { UINT16 tmp; tmp = (a); (a) = (b); (b) = tmp; } |  | 
 |  |  | 
 |  | // ---- 31khz | 
 |  |  | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | static REG8 bios0x18_30(REG8 rate, REG8 scrn) { | 
 |  |  | 
 |  | int                     crt; | 
 |  | int                     master; | 
 |  | int                     slave; | 
 |  | const CRTDATA   *p; | 
 |  |  | 
 |  | if (((rate & 0xf8) != 0x08) || (scrn & (~0x33)) || ((scrn & 3) == 3)) { | 
 |  | return(0); | 
 |  | } | 
 |  | if ((scrn & 0x30) == 0x30) {                            // 640x480 | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | if (rate & 4) { | 
 |  | gdc_analogext(TRUE); | 
 |  | mem[MEMB_PRXDUPD] |= 0x80; | 
 |  | crt = 4; | 
 |  | master = 3; | 
 |  | slave = 1; | 
 |  | gdc.display |= 0x10; | 
 |  | } | 
 |  | else | 
 |  | #endif | 
 |  | return(0); | 
 |  | } | 
 |  | else { | 
 |  | if ((scrn & 3) >= 2) { | 
 |  | return(0); | 
 |  | } | 
 |  | if (rate & 4) {                                                 // 31khz | 
 |  | crt = 2; | 
 |  | master = 2; | 
 |  | slave = 4; | 
 |  | } | 
 |  | else if (mem[MEMB_PRXCRT] & 0x40) {             // 24khz | 
 |  | crt = 2; | 
 |  | master = 1; | 
 |  | slave = 2; | 
 |  | } | 
 |  | else { | 
 |  | crt = 0; | 
 |  | master = 0; | 
 |  | slave = 0; | 
 |  | } | 
 |  | if ((scrn & 0x20) && (mem[MEMB_PRXDUPD] & 0x04)) { | 
 |  | slave += 1; | 
 |  | } | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | else { | 
 |  | gdc_analogext(FALSE); | 
 |  | mem[MEMB_PRXDUPD] &= ~0x80; | 
 |  | } | 
 |  | #endif | 
 |  | } | 
 |  | crt += (scrn & 3); | 
 |  | master += (scrn & 3); | 
 |  |  | 
 |  | if (rate & 4) { | 
 |  | gdc.display |= (1 << GDCDISP_31); | 
 |  | } | 
 |  | else { | 
 |  | gdc.display &= ~(1 << GDCDISP_31); | 
 |  | } | 
 |  |  | 
 |  | CopyMemory(gdc.m.para + GDC_SYNC, gdcmastersync[master], 8); | 
 |  | ZeroMemory(gdc.m.para + GDC_SCROLL, 8); | 
 |  | gdc.m.para[GDC_PITCH] = 80; | 
 |  |  | 
 |  | p = crtdata + crt; | 
 |  | gdc.m.para[GDC_CSRFORM + 0] = p->raster; | 
 |  | gdc.m.para[GDC_CSRFORM + 1] = 0; | 
 |  | gdc.m.para[GDC_CSRFORM + 2] = (p->raster << 3) + 3; | 
 |  | crtc.reg.pl = p->pl; | 
 |  | crtc.reg.bl = p->bl; | 
 |  | crtc.reg.cl = p->cl; | 
 |  | crtc.reg.ssl = 0; | 
 |  | crtc.reg.sur = 1; | 
 |  | crtc.reg.sdr = 0; | 
 |  |  | 
 |  | CopyMemory(gdc.s.para + GDC_SYNC, gdcslavesync[slave], 8); | 
 |  | ZeroMemory(gdc.s.para + GDC_SCROLL, 8); | 
 |  | if (slave & 1) { | 
 |  | gdc.s.para[GDC_PITCH] = 80; | 
 |  | gdc.clock |= 3; | 
 |  | mem[MEMB_PRXDUPD] |= 0x04; | 
 |  | } | 
 |  | else { | 
 |  | gdc.s.para[GDC_PITCH] = 40; | 
 |  | gdc.clock &= ~3; | 
 |  | mem[MEMB_PRXDUPD] &= ~0x04; | 
 |  | } | 
 |  | if ((scrn & 0x30) == 0x10) { | 
 |  | gdc.s.para[GDC_SCROLL+0] = (200*40) & 0xff; | 
 |  | gdc.s.para[GDC_SCROLL+1] = (200*40) >> 8; | 
 |  | } | 
 |  | if ((scrn & 0x20) || (!(mem[MEMB_PRXCRT] & 0x40))) { | 
 |  | gdc.mode1 &= ~(0x10); | 
 |  | gdc.s.para[GDC_CSRFORM] = 0; | 
 |  | } | 
 |  | else { | 
 |  | gdc.mode1 |= 0x10; | 
 |  | gdc.s.para[GDC_CSRFORM] = 1; | 
 |  | } | 
 |  |  | 
 |  | gdcs.textdisp &= ~GDCSCRN_ENABLE; | 
 |  | gdcs.textdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2; | 
 |  | gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2; | 
 |  | screenupdate |= 2; | 
 |  |  | 
 |  | mem[0x597] &= ~3; | 
 |  | mem[0x597] |= (scrn >> 4) & 3; | 
 |  | mem[MEMB_CRT_STS_FLAG] &= ~0x11; | 
 |  | if (!(scrn & 1)) { | 
 |  | mem[MEMB_CRT_STS_FLAG] |= 0x01; | 
 |  | } | 
 |  | if (scrn & 2) { | 
 |  | mem[MEMB_CRT_STS_FLAG] |= 0x10; | 
 |  | } | 
 |  | return(5);                      // 最後にGDCへ送ったデータ… | 
 |  | } | 
 |  |  | 
 |  | static REG8 bios0x18_31al(void) { | 
 |  |  | 
 |  | UINT8   rate; | 
 |  |  | 
 |  | rate = 0x08 + ((gdc.display >> (GDCDISP_31 - 5)) & 4); | 
 |  | return(rate); | 
 |  | } | 
 |  |  | 
 |  | static REG8 bios0x18_31bh(void) { | 
 |  |  | 
 |  | UINT8   scrn; | 
 |  |  | 
 |  | scrn = (mem[0x597] & 3) << 4; | 
 |  | if (!(mem[MEMB_CRT_STS_FLAG] & 0x01)) { | 
 |  | scrn |= 0x01; | 
 |  | } | 
 |  | if (mem[MEMB_CRT_STS_FLAG] & 0x10) { | 
 |  | scrn |= 0x02; | 
 |  | } | 
 |  | return(scrn); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 |  | // ---- slave | 
 |  |  | 
 |  | void bios0x18_40(void) { | 
 |  |  | 
 |  | gdc_forceready(GDCWORK_SLAVE); | 
 |  | if (!(gdcs.grphdisp & GDCSCRN_ENABLE)) { | 
 |  | gdcs.grphdisp |= GDCSCRN_ENABLE; | 
 |  | screenupdate |= 2; | 
 |  | } | 
 |  | mem[MEMB_PRXCRT] |= 0x80; | 
 |  | } | 
 |  |  | 
 |  | void bios0x18_41(void) { | 
 |  |  | 
 |  | gdc_forceready(GDCWORK_SLAVE); | 
 |  | if (gdcs.grphdisp & GDCSCRN_ENABLE) { | 
 |  | gdcs.grphdisp &= ~(GDCSCRN_ENABLE); | 
 |  | screenupdate |= 2; | 
 |  | } | 
 |  | mem[MEMB_PRXCRT] &= 0x7f; | 
 |  | } | 
 |  |  | 
 |  | void bios0x18_42(REG8 mode) { | 
 |  |  | 
 |  | UINT8   crtmode; | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | UINT8   rate; | 
 |  | UINT8   scrn; | 
 |  | #endif | 
 |  | int             slave; | 
 |  |  | 
 |  | gdc_forceready(GDCWORK_MASTER); | 
 |  | gdc_forceready(GDCWORK_SLAVE); | 
 |  |  | 
 |  | crtmode = modenum[mode >> 6]; | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | rate = bios0x18_31al(); | 
 |  | scrn = bios0x18_31bh(); | 
 |  | if ((mem[MEMB_CRT_BIOS] & 0x80) && | 
 |  | (((scrn & 0x30) == 0x30) || (crtmode == 3))) { | 
 |  | bios0x18_30(rate, (crtmode << 4) + 1); | 
 |  | } | 
 |  | else { | 
 |  | #endif | 
 |  | ZeroMemory(gdc.s.para + GDC_SCROLL, 8); | 
 |  | if (crtmode == 2) {                                                     // ALL | 
 |  | crtmode = 2; | 
 |  | if ((mem[MEMB_PRXDUPD] & 0x24) == 0x20) { | 
 |  | mem[MEMB_PRXDUPD] ^= 4; | 
 |  | gdc.clock |= 3; | 
 |  | CopyMemory(gdc.s.para + GDC_SYNC, gdcslavesync[3], 8); | 
 |  | gdc.s.para[GDC_PITCH] = 80; | 
 |  | gdcs.grphdisp |= GDCSCRN_EXT; | 
 |  | mem[MEMB_PRXDUPD] |= 0x08; | 
 |  | } | 
 |  | } | 
 |  | else { | 
 |  | if ((mem[MEMB_PRXDUPD] & 0x24) == 0x24) { | 
 |  | mem[MEMB_PRXDUPD] ^= 4; | 
 |  | gdc.clock &= ~3; | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | if (rate & 4) slave = 4; | 
 |  | else | 
 |  | #endif | 
 |  | slave = (mem[MEMB_PRXCRT] & 0x40)?2:0; | 
 |  | CopyMemory(gdc.s.para + GDC_SYNC, gdcslavesync[slave], 8); | 
 |  | gdc.s.para[GDC_PITCH] = 40; | 
 |  | gdcs.grphdisp |= GDCSCRN_EXT; | 
 |  | mem[MEMB_PRXDUPD] |= 0x08; | 
 |  | } | 
 |  | if (crtmode & 1) {                              // UPPER | 
 |  | gdc.s.para[GDC_SCROLL+0] = (200*40) & 0xff; | 
 |  | gdc.s.para[GDC_SCROLL+1] = (200*40) >> 8; | 
 |  | } | 
 |  | } | 
 |  | if ((crtmode == 2) || (!(mem[MEMB_PRXCRT] & 0x40))) { | 
 |  | gdc.mode1 &= ~(0x10); | 
 |  | gdc.s.para[GDC_CSRFORM] = 0; | 
 |  | } | 
 |  | else { | 
 |  | gdc.mode1 |= 0x10; | 
 |  | gdc.s.para[GDC_CSRFORM] = 1; | 
 |  | } | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | mem[MEMB_CRT_BIOS] &= ~3; | 
 |  | mem[MEMB_CRT_BIOS] |= crtmode; | 
 |  | } | 
 |  | #endif | 
 |  | if (crtmode != 3) { | 
 |  | gdcs.disp = (mode >> 4) & 1; | 
 |  | } | 
 |  | if (!(mode & 0x20)) { | 
 |  | gdc.mode1 &= ~0x04; | 
 |  | } | 
 |  | else { | 
 |  | gdc.mode2 |= 0x04; | 
 |  | } | 
 |  | gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | 
 |  | screenupdate |= 2; | 
 |  | } | 
 |  |  | 
| static void setbiosgdc(UINT32 csrw, const GDCVECT *vect, UINT vcnt, | static void setbiosgdc(UINT32 csrw, const GDCVECT *vect, UINT8 ope) { | 
| UINT8 ope) { |  | 
 |  |  | 
 | gdc.s.para[GDC_CSRW + 0] = (BYTE)csrw; | gdc.s.para[GDC_CSRW + 0] = (BYTE)csrw; | 
 | gdc.s.para[GDC_CSRW + 1] = (BYTE)(csrw >> 8); | gdc.s.para[GDC_CSRW + 1] = (BYTE)(csrw >> 8); | 
 | gdc.s.para[GDC_CSRW + 2] = (BYTE)(csrw >> 16); | gdc.s.para[GDC_CSRW + 2] = (BYTE)(csrw >> 16); | 
 |  |  | 
| vcnt = min(vcnt, 11); | gdc.s.para[GDC_VECTW] = vect->ope; | 
| if (vcnt) { | gdc_vectreset(&gdc.s); | 
| CopyMemory(gdc.s.para + GDC_VECTW, vect, vcnt); |  | 
| } |  | 
 |  |  | 
 | gdc.s.para[GDC_WRITE] = ope; | gdc.s.para[GDC_WRITE] = ope; | 
 | mem[MEMB_PRXDUPD] &= ~3; | mem[MEMB_PRXDUPD] &= ~3; | 
 | mem[MEMB_PRXDUPD] |= ope; | mem[MEMB_PRXDUPD] |= ope; | 
 | } | } | 
 |  |  | 
|  | static void bios0x18_47(void) { | 
| static void bios18_47(void) { |  | 
 |  |  | 
 | UCWTBL          ucw; | UCWTBL          ucw; | 
 | GDCVECT         vect; | GDCVECT         vect; | 
| Line 145  static void bios18_47(void) { | Line 560  static void bios18_47(void) { | 
 | SINT16          dx; | SINT16          dx; | 
 | SINT16          dy; | SINT16          dy; | 
 |  |  | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_SLAVE); | 
| if (gdc.s.cnt) { |  | 
| gdc_work(GDCWORK_SLAVE); |  | 
| } |  | 
| gdc_forceready(&gdc.s); |  | 
|  |  | 
 | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | 
 |  |  | 
 | GBSX1 = LOADINTELWORD(ucw.GBSX1); | GBSX1 = LOADINTELWORD(ucw.GBSX1); | 
 | GBSY1 = LOADINTELWORD(ucw.GBSY1); | GBSY1 = LOADINTELWORD(ucw.GBSY1); | 
 | GBSX2 = LOADINTELWORD(ucw.GBSX2); | GBSX2 = LOADINTELWORD(ucw.GBSX2); | 
| Line 162  static void bios18_47(void) { | Line 571  static void bios18_47(void) { | 
 | data2 = 0; | data2 = 0; | 
 | if (ucw.GBDTYP == 0x01) { | if (ucw.GBDTYP == 0x01) { | 
 | func = gdcsub_vectl; | func = gdcsub_vectl; | 
| if ((GBSX1 > GBSX2) || | gdcsub_setvectl(&vect, GBSX1, GBSY1, GBSX2, GBSY2); | 
| ((GBSX1 == GBSX2) && (GBSY1 > GBSY2))) { |  | 
| SWAPU16(GBSX1, GBSX2); |  | 
| SWAPU16(GBSY1, GBSY2); |  | 
| } |  | 
| dx = GBSX2 - GBSX1; |  | 
| dy = GBSY2 - GBSY1; |  | 
| if (dy > 0) { |  | 
| if (dx < dy) { |  | 
| vect.ope = 0; |  | 
| SWAPU16(dx, dy); |  | 
| } |  | 
| else { |  | 
| vect.ope = 1; |  | 
| } |  | 
| } |  | 
| else { |  | 
| dy = -dy; |  | 
| if (dx > dy) { |  | 
| vect.ope = 2; |  | 
| } |  | 
| else { |  | 
| vect.ope = 3; |  | 
| SWAPU16(dx, dy); |  | 
| } |  | 
| } |  | 
| vect.ope += 0x08; |  | 
| STOREINTELWORD(vect.DC, dx); |  | 
| data = dy * 2; |  | 
| STOREINTELWORD(vect.D1, data); |  | 
| data -= dx; |  | 
| STOREINTELWORD(vect.D, data); |  | 
| data -= dx; |  | 
| STOREINTELWORD(vect.D2, data); |  | 
 | } | } | 
 | else if (ucw.GBDTYP <= 0x02) { | else if (ucw.GBDTYP <= 0x02) { | 
 | func = gdcsub_vectr; | func = gdcsub_vectr; | 
| Line 278  static void bios18_47(void) { | Line 654  static void bios18_47(void) { | 
 |  |  | 
 | // 最後に使った奴を記憶 | // 最後に使った奴を記憶 | 
 | *(UINT16 *)(mem + MEMW_PRXGLS) = *(UINT16 *)(ucw.GBMDOTI); | *(UINT16 *)(mem + MEMW_PRXGLS) = *(UINT16 *)(ucw.GBMDOTI); | 
| *(UINT16 *)(gdc.s.para + GDC_TEXTW) = *(UINT16 *)(ucw.GBMDOTI); | STOREINTELWORD(mem + GDC_TEXTW, GBMDOTI); | 
| setbiosgdc(csrw, &vect, (ucw.GBDTYP != 0x01)?11:9, ope); | setbiosgdc(csrw, &vect, ope); | 
 | } | } | 
 |  |  | 
| static void bios18_49(void) { | static void bios0x18_49(void) { | 
 |  |  | 
 | UCWTBL          ucw; | UCWTBL          ucw; | 
 | UINT            i; | UINT            i; | 
| Line 294  static void bios18_49(void) { | Line 670  static void bios18_49(void) { | 
 | UINT32          csrw; | UINT32          csrw; | 
 | UINT8           ope; | UINT8           ope; | 
 |  |  | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_SLAVE); | 
| if (gdc.s.cnt) { |  | 
| gdc_work(GDCWORK_SLAVE); |  | 
| } |  | 
| gdc_forceready(&gdc.s); |  | 
 |  |  | 
 | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | 
 | for (i=0; i<8; i++) { | for (i=0; i<8; i++) { | 
| Line 315  static void bios18_49(void) { | Line 687  static void bios18_49(void) { | 
 | } | } | 
 | else { | else { | 
 | STOREINTELWORD(vect.DC, 7); | STOREINTELWORD(vect.DC, 7); | 
| vect.D[0] = gdc.s.para[GDC_VECTW + 3]; | STOREINTELWORD(vect.D, 7); | 
| vect.D[1] = gdc.s.para[GDC_VECTW + 4]; |  | 
 | } | } | 
 |  |  | 
 | GBSX1 = LOADINTELWORD(ucw.GBSX1); | GBSX1 = LOADINTELWORD(ucw.GBSX1); | 
| Line 342  static void bios18_49(void) { | Line 713  static void bios18_49(void) { | 
 | } | } | 
 |  |  | 
 | // 最後に使った奴を記憶 | // 最後に使った奴を記憶 | 
| setbiosgdc(csrw, &vect, 5, ope); | setbiosgdc(csrw, &vect, ope); | 
 | } | } | 
 |  |  | 
 |  |  | 
 |  | // ---- PC-9821 | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static void bios0x18_4d(REG8 mode) { | 
 |  |  | 
 |  | if ((mem[0x45c] & 0x40) && | 
 |  | ((mem[MEMB_CRT_BIOS] & 3) == 2)) { | 
 |  | if (mode == 0) { | 
 |  | gdc_analogext(FALSE); | 
 |  | mem[MEMB_PRXDUPD] &= ~0x7f; | 
 |  | mem[MEMB_PRXDUPD] |= 0x04; | 
 |  | } | 
 |  | else if (mode == 1) { | 
 |  | gdc_analogext(TRUE); | 
 |  | mem[MEMB_PRXDUPD] |= 0x80; | 
 |  | } | 
 |  | else { | 
 |  | mem[MEMB_PRXDUPD] |= 0x04; | 
 |  | } | 
 |  | } | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 | // ---- | // ---- | 
 |  |  | 
 | void bios0x18(void) { | void bios0x18(void) { | 
 |  |  | 
 | union { | union { | 
 | BOOL    b; | BOOL    b; | 
 |  | REG8    r8; | 
 | UINT16  w; | UINT16  w; | 
 | UINT32  d; | UINT32  d; | 
| const CRTDATA   *crt; | UINT8   col[4]; | 
 | }               tmp; | }               tmp; | 
 |  |  | 
 | UINT    pos; |  | 
 | BYTE    buf[34]; |  | 
 | BYTE    *p; |  | 
 | int             i; | int             i; | 
 |  |  | 
| #if 0 | #if 1 | 
 | TRACEOUT(("int18 AX=%.4x %.4x:%.4x", CPU_AX, | TRACEOUT(("int18 AX=%.4x %.4x:%.4x", CPU_AX, | 
 | i286_memword_read(CPU_SS, CPU_SP+2), | i286_memword_read(CPU_SS, CPU_SP+2), | 
 | i286_memword_read(CPU_SS, CPU_SP))); | i286_memword_read(CPU_SS, CPU_SP))); | 
| Line 424  const CRTDATA *crt; | Line 816  const CRTDATA *crt; | 
 | } | } | 
 | break; | break; | 
 |  |  | 
| case 0x0a:                                              // CRTモードの設定 | case 0x0a:                                              // CRTモードの設定(15/24khz) | 
| // GDCバッファを空に | bios0x18_0a(CPU_AL); | 
| if (gdc.m.cnt) { |  | 
| gdc_work(GDCWORK_MASTER); |  | 
| } |  | 
| gdc_forceready(&gdc.m); |  | 
|  |  | 
| gdc.mode1 &= ~(0x2d); |  | 
| mem[MEMB_CRT_STS_FLAG] = CPU_AL; |  | 
| tmp.crt = crtdata; |  | 
| if (!(np2cfg.dipsw[0] & 1)) { |  | 
| mem[MEMB_CRT_STS_FLAG] |= 0x80; |  | 
| gdc.mode1 |= 0x08; |  | 
| tmp.crt += 2; |  | 
| } |  | 
| if (CPU_AL & 0x01) { |  | 
| tmp.crt += 1;                                   // 20行 |  | 
| } |  | 
| if (CPU_AL & 0x02) { |  | 
| gdc.mode1 |= 0x04;                              // 40桁 |  | 
| } |  | 
| if (CPU_AL & 0x04) { |  | 
| gdc.mode1 |= 0x01;                              // アトリビュート |  | 
| } |  | 
| if (CPU_AL & 0x08) { |  | 
| gdc.mode1 |= 0x20;                              // コードアクセス |  | 
| } |  | 
| mem[MEMB_CRT_RASTER] = tmp.crt->raster; |  | 
| crtc.reg.pl = tmp.crt->pl; |  | 
| crtc.reg.bl = tmp.crt->bl; |  | 
| crtc.reg.cl = tmp.crt->cl; |  | 
| crtc.reg.ssl = 0; |  | 
| gdc_restorekacmode(); |  | 
| bios0x18_10(0); |  | 
 | break; | break; | 
 |  |  | 
 | case 0x0b:                                              // CRTモードのセンス | case 0x0b:                                              // CRTモードのセンス | 
| Line 479  const CRTDATA *crt; | Line 839  const CRTDATA *crt; | 
 | break; | break; | 
 |  |  | 
 | case 0x0e:                                              // 一つの表示領域の設定 | case 0x0e:                                              // 一つの表示領域の設定 | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); | 
| if (gdc.m.cnt) { |  | 
| gdc_work(GDCWORK_MASTER); |  | 
| } |  | 
| gdc_forceready(&gdc.m); |  | 
|  |  | 
 | ZeroMemory(&gdc.m.para[GDC_SCROLL], 16); | ZeroMemory(&gdc.m.para[GDC_SCROLL], 16); | 
 | tmp.w = CPU_DX >> 1; | tmp.w = CPU_DX >> 1; | 
 | SETBIOSMEM16(MEMW_CRT_W_VRAMADR, tmp.w); | SETBIOSMEM16(MEMW_CRT_W_VRAMADR, tmp.w); | 
| Line 496  const CRTDATA *crt; | Line 851  const CRTDATA *crt; | 
 | SETBIOSMEM16(MEMW_CRT_W_RASTER, tmp.w); | SETBIOSMEM16(MEMW_CRT_W_RASTER, tmp.w); | 
 | STOREINTELWORD(gdc.m.para + GDC_SCROLL + 2, tmp.w); | STOREINTELWORD(gdc.m.para + GDC_SCROLL + 2, tmp.w); | 
 | gdcs.textdisp |= GDCSCRN_ALLDRAW2; | gdcs.textdisp |= GDCSCRN_ALLDRAW2; | 
| screenupdate |= 2; | //                      screenupdate |= 2; | 
 | break; | break; | 
 |  |  | 
 | case 0x0f:                                              // 複数の表示領域の設定 | case 0x0f:                                              // 複数の表示領域の設定 | 
| SETBIOSMEM16(0x0053e, CPU_CX); | gdc_forceready(GDCWORK_MASTER); | 
| SETBIOSMEM16(0x00540, CPU_BX); | bios0x18_0f(CPU_BX, CPU_CX, CPU_DH, CPU_DL); | 
| mem[0x00547] = CPU_DH; |  | 
| mem[0x0053D] = CPU_DL; |  | 
| // wait sync int |  | 
| if ((i = CPU_DL) > 0) { |  | 
| pos = CPU_CX; |  | 
| p = gdc.m.para + GDC_SCROLL + (CPU_DH << 2); |  | 
| while((i--) && (p < (gdc.m.para + GDC_SCROLL + 0x10))) { |  | 
| REG16 t; |  | 
| t = i286_memword_read(CPU_BX, pos); |  | 
| t >>= 1; |  | 
| STOREINTELWORD(p, t); |  | 
| t = i286_memword_read(CPU_BX, pos + 2); |  | 
| if (!(mem[MEMB_CRT_STS_FLAG] & 0x01)) {         // 25 |  | 
| t *= (16 * 16); |  | 
| } |  | 
| else {                                                                          // 20 |  | 
| t *= (20 * 16); |  | 
| } |  | 
| if (!(mem[MEMB_CRT_STS_FLAG] & 0x80)) { |  | 
| t >>= 1; |  | 
| } |  | 
| STOREINTELWORD(p + 2, t); |  | 
| pos += 4; |  | 
| p += 4; |  | 
| } |  | 
| } |  | 
| gdcs.textdisp |= GDCSCRN_ALLDRAW2; |  | 
| screenupdate |= 2; |  | 
 | break; | break; | 
 |  |  | 
| case 0x10:                                              // カーソルタイプの設定 | case 0x10:                                              // カーソルタイプの設定(15/24khz) | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); | 
| if (gdc.m.cnt) { |  | 
| gdc_work(GDCWORK_MASTER); |  | 
| } |  | 
| gdc_forceready(&gdc.m); |  | 
|  |  | 
 | bios0x18_10((REG8)(CPU_AL & 1)); | bios0x18_10((REG8)(CPU_AL & 1)); | 
 | break; | break; | 
 |  |  | 
 | case 0x11:                                              // カーソルの表示開始 | case 0x11:                                              // カーソルの表示開始 | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); | 
| if (gdc.m.cnt) { |  | 
| gdc_work(GDCWORK_MASTER); |  | 
| } |  | 
| gdc_forceready(&gdc.m); |  | 
|  |  | 
 | if (gdc.m.para[GDC_CSRFORM] != (mem[MEMB_CRT_RASTER] | 0x80)) { | if (gdc.m.para[GDC_CSRFORM] != (mem[MEMB_CRT_RASTER] | 0x80)) { | 
 | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER] | 0x80; | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER] | 0x80; | 
 | } | } | 
| Line 556  const CRTDATA *crt; | Line 873  const CRTDATA *crt; | 
 | break; | break; | 
 |  |  | 
 | case 0x12:                                              // カーソルの表示停止 | case 0x12:                                              // カーソルの表示停止 | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); | 
| if (gdc.m.cnt) { |  | 
| gdc_work(GDCWORK_MASTER); |  | 
| } |  | 
| gdc_forceready(&gdc.m); |  | 
|  |  | 
 | if (gdc.m.para[GDC_CSRFORM] != mem[MEMB_CRT_RASTER]) { | if (gdc.m.para[GDC_CSRFORM] != mem[MEMB_CRT_RASTER]) { | 
 | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER]; | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER]; | 
 | gdcs.textdisp |= GDCSCRN_ALLDRAW | GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_ALLDRAW | GDCSCRN_EXT; | 
| Line 569  const CRTDATA *crt; | Line 881  const CRTDATA *crt; | 
 | break; | break; | 
 |  |  | 
 | case 0x13:                                              // カーソル位置の設定 | case 0x13:                                              // カーソル位置の設定 | 
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); | 
| if (gdc.m.cnt) { |  | 
| gdc_work(GDCWORK_MASTER); |  | 
| } |  | 
| gdc_forceready(&gdc.m); |  | 
|  |  | 
 | tmp.w = CPU_DX >> 1; | tmp.w = CPU_DX >> 1; | 
 | if (LOADINTELWORD(gdc.m.para + GDC_CSRW) != tmp.w) { | if (LOADINTELWORD(gdc.m.para + GDC_CSRW) != tmp.w) { | 
 | STOREINTELWORD(gdc.m.para + GDC_CSRW, tmp.w); | STOREINTELWORD(gdc.m.para + GDC_CSRW, tmp.w); | 
| Line 583  const CRTDATA *crt; | Line 890  const CRTDATA *crt; | 
 | break; | break; | 
 |  |  | 
 | case 0x14:                                              // フォントパターンの読み出し | case 0x14:                                              // フォントパターンの読み出し | 
| switch(CPU_DH) { | bios0x18_14(CPU_BX, CPU_CX, CPU_DX); | 
| case 0x00:                      // 8x8 |  | 
| i286_memword_write(CPU_BX, CPU_CX, 0x0101); |  | 
| i286_memstr_write(CPU_BX, CPU_CX + 2, |  | 
| fontrom + 0x82000 + (CPU_DL << 4), 8); |  | 
| break; |  | 
|  |  | 
| case 0x28:                      // 8x16 KANJI |  | 
| case 0x29: |  | 
| case 0x2a: |  | 
| case 0x2b: |  | 
| i286_memword_write(CPU_BX, CPU_CX, 0x0102); |  | 
| i286_memstr_write(CPU_BX, CPU_CX + 2, |  | 
| fontrom + ((CPU_DL & 0x7f) << 12) |  | 
| + ((CPU_DH - 0x20) << 4), 16); |  | 
| break; |  | 
|  |  | 
| case 0x80:                      // 8x16 ANK |  | 
| i286_memword_write(CPU_BX, CPU_CX, 0x0102); |  | 
| i286_memstr_write(CPU_BX, CPU_CX + 2, |  | 
| fontrom + 0x80000 + (CPU_DL << 4), 16); |  | 
| break; |  | 
|  |  | 
| default: |  | 
| buf[0] = 0x02; |  | 
| buf[1] = 0x02; |  | 
| p = fontrom + ((CPU_DL & 0x7f) << 12) |  | 
| + (((CPU_DH - 0x20) & 0x7f) << 4); |  | 
| for (i=1; i<17; i++, p++) { |  | 
| buf[i*2+0] = *p; |  | 
| buf[i*2+1] = *(p+0x800); |  | 
| } |  | 
| i286_memstr_write(CPU_BX, CPU_CX, buf, 34); |  | 
| break; |  | 
| } |  | 
 | break; | break; | 
 |  |  | 
 | case 0x15:                                              // ライトペン位置読みだし | case 0x15:                                              // ライトペン位置読みだし | 
| Line 639  const CRTDATA *crt; | Line 912  const CRTDATA *crt; | 
 | break; | break; | 
 |  |  | 
 | case 0x1a:                                              // ユーザー文字の定義 | case 0x1a:                                              // ユーザー文字の定義 | 
| if ((CPU_DH & 0x7e) == 0x76) { | bios0x18_1a(CPU_BX, CPU_CX, CPU_DX); | 
| i286_memstr_read(CPU_BX, CPU_CX + 2, buf, 32); |  | 
| p = fontrom + ((CPU_DL & 0x7f) << 12) |  | 
| + (((CPU_DH - 0x20) & 0x7f) << 4); |  | 
| for (i=0; i<16; i++, p++) { |  | 
| *p = buf[i*2+0]; |  | 
| *(p+0x800) = buf[i*2+1]; |  | 
| } |  | 
| cgwindow.writable |= 0x80; |  | 
| } |  | 
 | break; | break; | 
 |  |  | 
 | case 0x1b:                                              // KCGアクセスモードの設定 | case 0x1b:                                              // KCGアクセスモードの設定 | 
| Line 666  const CRTDATA *crt; | Line 930  const CRTDATA *crt; | 
 | break; | break; | 
 | } | } | 
 | break; | break; | 
|  | #if defined(SUPPORT_CRT31KHZ) | 
| case 0x40:                                              // グラフィック画面の表示開始 | case 0x30: | 
| // GDCバッファを空に | if (mem[MEMB_CRT_BIOS] & 0x80) { | 
| if (gdc.s.cnt) { | gdc_forceready(GDCWORK_MASTER); | 
| gdc_work(GDCWORK_SLAVE); | gdc_forceready(GDCWORK_SLAVE); | 
|  | tmp.r8 = bios0x18_30(CPU_AL, CPU_BH); | 
|  | CPU_AH = tmp.r8; | 
|  | if (tmp.r8 == 0x05) { | 
|  | CPU_AL = 0; | 
|  | CPU_BH = 0; | 
|  | TRACEOUT(("success")); | 
|  | } | 
|  | else { | 
|  | CPU_AL = 1; | 
|  | CPU_BH = 1; | 
|  | TRACEOUT(("failure")); | 
|  | } | 
 | } | } | 
| if (!(gdcs.grphdisp & GDCSCRN_ENABLE)) { | break; | 
| gdcs.grphdisp |= GDCSCRN_ENABLE; |  | 
| screenupdate |= 2; | case 0x31: | 
|  | if (mem[MEMB_CRT_BIOS] & 0x80) { | 
|  | CPU_AL = bios0x18_31al(); | 
|  | CPU_BH = bios0x18_31bh(); | 
 | } | } | 
| mem[MEMB_PRXCRT] |= 0x80; | break; | 
|  | #endif | 
|  | case 0x40:                                              // グラフィック画面の表示開始 | 
|  | bios0x18_40(); | 
 | break; | break; | 
 |  |  | 
 | case 0x41:                                              // グラフィック画面の表示終了 | case 0x41:                                              // グラフィック画面の表示終了 | 
| // GDCバッファを空に | bios0x18_41(); | 
| if (gdc.s.cnt) { |  | 
| gdc_work(GDCWORK_SLAVE); |  | 
| } |  | 
| gdc_forceready(&gdc.s); |  | 
| if (gdcs.grphdisp & GDCSCRN_ENABLE) { |  | 
| gdcs.grphdisp &= ~(GDCSCRN_ENABLE); |  | 
| screenupdate |= 2; |  | 
| } |  | 
| mem[MEMB_PRXCRT] &= 0x7f; |  | 
 | break; | break; | 
 |  |  | 
 | case 0x42:                                              // 表示領域の設定 | case 0x42:                                              // 表示領域の設定 | 
| // GDCバッファを空に | bios0x18_42(CPU_CH); | 
| if (gdc.s.cnt) { |  | 
| gdc_work(GDCWORK_SLAVE); |  | 
| } |  | 
| gdc_forceready(&gdc.s); |  | 
|  |  | 
| ZeroMemory(&gdc.s.para[GDC_SCROLL], 8); |  | 
| if ((CPU_CH & 0xc0) == 0xc0) {          // ALL |  | 
| tmp.b = FALSE; |  | 
| if ((mem[MEMB_PRXDUPD] & 0x24) == 0x20) { |  | 
| mem[MEMB_PRXDUPD] ^= 4; |  | 
| gdc.clock |= 3; |  | 
| CopyMemory(gdc.s.para + GDC_SYNC, sync400m, 8); |  | 
| gdc.s.para[GDC_PITCH] = 80; |  | 
| gdcs.grphdisp |= GDCSCRN_EXT; |  | 
| mem[MEMB_PRXDUPD] |= 0x08; |  | 
| } |  | 
| } |  | 
| else { |  | 
| tmp.b = TRUE; |  | 
| if ((mem[MEMB_PRXDUPD] & 0x24) == 0x24) { |  | 
| mem[MEMB_PRXDUPD] ^= 4; |  | 
| gdc.clock &= ~3; |  | 
| CopyMemory(gdc.s.para + GDC_SYNC, |  | 
| (mem[MEMB_PRXCRT] & 0x40)?sync200m:sync200l, 8); |  | 
| gdc.s.para[GDC_PITCH] = 40; |  | 
| gdcs.grphdisp |= GDCSCRN_EXT; |  | 
| mem[MEMB_PRXDUPD] |= 0x08; |  | 
| } |  | 
| if (CPU_CH & 0x40) {                    // UPPER |  | 
| gdc.s.para[GDC_SCROLL+0] = (200*40) & 0xff; |  | 
| gdc.s.para[GDC_SCROLL+1] = (200*40) >> 8; |  | 
| } |  | 
| } |  | 
| if ((!tmp.b) || (!(mem[MEMB_PRXCRT] & 0x40))) { |  | 
| gdc.mode1 &= ~(0x10); |  | 
| gdc.s.para[GDC_CSRFORM] = 0; |  | 
| } |  | 
| else { |  | 
| gdc.mode1 |= 0x10; |  | 
| gdc.s.para[GDC_CSRFORM] = 1; |  | 
| } |  | 
| gdcs.disp = (CPU_CH >> 4) & 1; |  | 
| gdcs.grphdisp |= GDCSCRN_ALLDRAW2; |  | 
| screenupdate |= 2; |  | 
 | break; | break; | 
 |  |  | 
 | case 0x43:                                              // パレットの設定 | case 0x43:                                              // パレットの設定 | 
 | i286_memstr_read(CPU_DS, CPU_BX + offsetof(UCWTBL, GBCPC), | i286_memstr_read(CPU_DS, CPU_BX + offsetof(UCWTBL, GBCPC), | 
| buf, 4); | tmp.col, 4); | 
| tmp.d = LOADINTELDWORD(buf); | for (i=0; i<4; i++) { | 
| for (i=8; i--;) { | gdc_setdegitalpal(6 - (i*2), (REG8)(tmp.col[i] >> 4)); | 
| gdc_setdegitalpal(i, (REG8)(tmp.d & 15)); | gdc_setdegitalpal(7 - (i*2), (REG8)(tmp.col[i] & 15)); | 
| tmp.d >>= 4; |  | 
 | } | } | 
 | break; | break; | 
 |  |  | 
| Line 756  const CRTDATA *crt; | Line 984  const CRTDATA *crt; | 
 | //                      } | //                      } | 
 | break; | break; | 
 |  |  | 
 |  | case 0x45: | 
 |  | case 0x46: | 
 |  | TRACEOUT(("unsupport bios 18-%.2x", CPU_AH)); | 
 |  | break; | 
 |  |  | 
 | case 0x47:                                              // 直線、矩形の描画 | case 0x47:                                              // 直線、矩形の描画 | 
 | case 0x48:                                              // 円の描画 | case 0x48:                                              // 円の描画 | 
| bios18_47(); | bios0x18_47(); | 
 | break; | break; | 
 |  |  | 
 | case 0x49:                                              // グラフィック文字の描画 | case 0x49:                                              // グラフィック文字の描画 | 
| bios18_49(); | bios0x18_49(); | 
 | break; | break; | 
 |  |  | 
 | case 0x4a:                                              // 描画モードの設定 | case 0x4a:                                              // 描画モードの設定 | 
| Line 777  const CRTDATA *crt; | Line 1010  const CRTDATA *crt; | 
 | } | } | 
 | } | } | 
 | break; | break; | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | case 0x4d: | 
 |  | bios0x18_4d(CPU_CH); | 
 |  | break; | 
 |  | #endif | 
 | } | } | 
 | } | } | 
 |  |  |