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| version 1.14, 2004/02/11 04:22:18 | version 1.18, 2004/02/16 05:09:00 |
|---|---|
| Line 52 static const CSRFORM csrform[4] = { | Line 52 static const CSRFORM csrform[4] = { |
| {0x07, 0x3b}, {0x09, 0x4b}, | {0x07, 0x3b}, {0x09, 0x4b}, |
| {0x0f, 0x7b}, {0x13, 0x9b}}; | {0x0f, 0x7b}, {0x13, 0x9b}}; |
| static const UINT8 sync200l[8] = {0x02,0x26,0x03,0x11,0x86,0x0f,0xc8,0x84}; | static const UINT8 sync200l[8] = {0x02,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94}; |
| static const UINT8 sync200m[8] = {0x02,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; | static const UINT8 sync200m[8] = {0x02,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; |
| static const UINT8 sync400m[8] = {0x02,0x4e,0x07,0x25,0x87,0x07,0x90,0x65}; | static const UINT8 sync400m[8] = {0x02,0x4e,0x07,0x25,0x87,0x07,0x90,0x65}; |
| Line 93 static void bios0x18_10(REG8 curdel) { | Line 93 static void bios0x18_10(REG8 curdel) { |
| gdcs.textdisp |= GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; |
| } | } |
| void bios0x18_16(BYTE chr, BYTE atr) { | void bios0x18_0a(REG8 mode) { |
| const CRTDATA *crt; | |
| // GDCバッファを空に | |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| gdc.mode1 &= ~(0x2d); | |
| mem[MEMB_CRT_STS_FLAG] = mode; | |
| crt = crtdata; | |
| if (!(np2cfg.dipsw[0] & 1)) { | |
| mem[MEMB_CRT_STS_FLAG] |= 0x80; | |
| gdc.mode1 |= 0x08; | |
| crt += 2; | |
| } | |
| if (mode & 0x01) { | |
| crt += 1; // 20行 | |
| } | |
| if (mode & 0x02) { | |
| gdc.mode1 |= 0x04; // 40桁 | |
| } | |
| if (mode & 0x04) { | |
| gdc.mode1 |= 0x01; // アトリビュート | |
| } | |
| if (mode & 0x08) { | |
| gdc.mode1 |= 0x20; // コードアクセス | |
| } | |
| mem[MEMB_CRT_RASTER] = crt->raster; | |
| crtc.reg.pl = crt->pl; | |
| crtc.reg.bl = crt->bl; | |
| crtc.reg.cl = crt->cl; | |
| crtc.reg.ssl = 0; | |
| gdc_restorekacmode(); | |
| bios0x18_10(0); | |
| } | |
| void bios0x18_16(REG8 chr, REG8 atr) { | |
| UINT32 i; | UINT32 i; |
| Line 109 void bios0x18_16(BYTE chr, BYTE atr) { | Line 148 void bios0x18_16(BYTE chr, BYTE atr) { |
| #define SWAPU16(a, b) { UINT16 tmp; tmp = (a); (a) = (b); (b) = tmp; } | #define SWAPU16(a, b) { UINT16 tmp; tmp = (a); (a) = (b); (b) = tmp; } |
| static REG8 swapbit(REG8 bit) { | |
| REG8 ret; | static void setbiosgdc(UINT32 csrw, const GDCVECT *vect, UINT vcnt, |
| UINT8 ope) { | |
| ret = 0; | gdc.s.para[GDC_CSRW + 0] = (BYTE)csrw; |
| while(bit) { | gdc.s.para[GDC_CSRW + 1] = (BYTE)(csrw >> 8); |
| ret = (ret << 1) + (bit & 1); | gdc.s.para[GDC_CSRW + 2] = (BYTE)(csrw >> 16); |
| bit >>= 1; | |
| vcnt = min(vcnt, 11); | |
| if (vcnt) { | |
| CopyMemory(gdc.s.para + GDC_VECTW, vect, vcnt); | |
| } | } |
| return(ret); | |
| gdc.s.para[GDC_WRITE] = ope; | |
| mem[MEMB_PRXDUPD] &= ~3; | |
| mem[MEMB_PRXDUPD] |= ope; | |
| } | } |
| static void bios18_47(void) { | static void bios18_47(void) { |
| UCWTBL ucw; | UCWTBL ucw; |
| Line 151 static void bios18_47(void) { | Line 197 static void bios18_47(void) { |
| GBSX2 = LOADINTELWORD(ucw.GBSX2); | GBSX2 = LOADINTELWORD(ucw.GBSX2); |
| GBSY2 = LOADINTELWORD(ucw.GBSY2); | GBSY2 = LOADINTELWORD(ucw.GBSY2); |
| ZeroMemory(&vect, sizeof(vect)); | ZeroMemory(&vect, sizeof(vect)); |
| data = 0; | |
| data2 = 0; | |
| if (ucw.GBDTYP == 0x01) { | if (ucw.GBDTYP == 0x01) { |
| func = gdcsub_line; | func = gdcsub_vectl; |
| if ((GBSX1 > GBSX2) || | if ((GBSX1 > GBSX2) || |
| ((GBSX1 == GBSX2) && (GBSY1 > GBSY2))) { | ((GBSX1 == GBSX2) && (GBSY1 > GBSY2))) { |
| SWAPU16(GBSX1, GBSX2); | SWAPU16(GBSX1, GBSX2); |
| Line 189 static void bios18_47(void) { | Line 237 static void bios18_47(void) { |
| STOREINTELWORD(vect.D2, data); | STOREINTELWORD(vect.D2, data); |
| } | } |
| else if (ucw.GBDTYP <= 0x02) { | else if (ucw.GBDTYP <= 0x02) { |
| func = gdcsub_box; | func = gdcsub_vectr; |
| vect.ope = 0x40 + (ucw.GBDSP & 7); | vect.ope = 0x40 + (ucw.GBDSP & 7); |
| dx = GBSX2 - GBSX1; | dx = GBSX2 - GBSX1; |
| if (dx < 0) { | if (dx < 0) { |
| Line 231 static void bios18_47(void) { | Line 279 static void bios18_47(void) { |
| STOREINTELWORD(vect.DM, data); | STOREINTELWORD(vect.DM, data); |
| } | } |
| else { | else { |
| func = gdcsub_circle; | func = gdcsub_vectc; |
| vect.ope = 0x20 + (ucw.GBDSP & 7); | vect.ope = 0x20 + (ucw.GBDSP & 7); |
| vect.DC[0] = ucw.GBLNG1[0]; | vect.DC[0] = ucw.GBLNG1[0]; |
| vect.DC[1] = ucw.GBLNG1[1]; | vect.DC[1] = ucw.GBLNG1[1]; |
| Line 250 static void bios18_47(void) { | Line 298 static void bios18_47(void) { |
| } | } |
| csrw = (GBSY1 * 40) + (GBSX1 >> 4); | csrw = (GBSY1 * 40) + (GBSX1 >> 4); |
| csrw += (GBSX1 & 0xf) << 20; | csrw += (GBSX1 & 0xf) << 20; |
| GBMDOTI = (swapbit(ucw.GBMDOTI[0]) << 8) + swapbit(ucw.GBMDOTI[1]); | GBMDOTI = (GDCPATREVERSE(ucw.GBMDOTI[0]) << 8) + |
| GDCPATREVERSE(ucw.GBMDOTI[1]); | |
| if ((CPU_CH & 0x30) == 0x30) { | if ((CPU_CH & 0x30) == 0x30) { |
| ope = (ucw.GBON_PTN & 1)?GDCOPE_SET:GDCOPE_CLEAR; | ope = (ucw.GBON_PTN & 1)?GDCOPE_SET:GDCOPE_CLEAR; |
| func(csrw + 0x4000, &vect, GBMDOTI, ope); | func(csrw + 0x4000, &vect, GBMDOTI, ope); |
| Line 269 static void bios18_47(void) { | Line 318 static void bios18_47(void) { |
| // 最後に使った奴を記憶 | // 最後に使った奴を記憶 |
| *(UINT16 *)(mem + MEMW_PRXGLS) = *(UINT16 *)(ucw.GBMDOTI); | *(UINT16 *)(mem + MEMW_PRXGLS) = *(UINT16 *)(ucw.GBMDOTI); |
| *(UINT16 *)(gdc.s.para + GDC_TEXTW) = *(UINT16 *)(ucw.GBMDOTI); | *(UINT16 *)(gdc.s.para + GDC_TEXTW) = *(UINT16 *)(ucw.GBMDOTI); |
| setbiosgdc(csrw, &vect, (ucw.GBDTYP != 0x01)?11:9, ope); | |
| gdc.s.para[GDC_WRITE] = ope; | |
| mem[MEMB_PRXDUPD] &= ~3; | |
| mem[MEMB_PRXDUPD] |= ope; | |
| } | } |
| static void bios18_49(void) { | static void bios18_49(void) { |
| Line 296 static void bios18_49(void) { | Line 342 static void bios18_49(void) { |
| i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); |
| for (i=0; i<8; i++) { | for (i=0; i<8; i++) { |
| mem[MEMW_PRXGLS + i] = ucw.GBMDOTI[i]; | mem[MEMW_PRXGLS + i] = ucw.GBMDOTI[i]; |
| pat[i] = swapbit(ucw.GBMDOTI[i]); | pat[i] = GDCPATREVERSE(ucw.GBMDOTI[i]); |
| gdc.s.para[GDC_TEXTW + i] = pat[i]; | gdc.s.para[GDC_TEXTW + i] = pat[i]; |
| } | } |
| vect.ope = 0x10 + (ucw.GBDSP & 7); | vect.ope = 0x10 + (ucw.GBDSP & 7); |
| Line 335 static void bios18_49(void) { | Line 381 static void bios18_49(void) { |
| } | } |
| // 最後に使った奴を記憶 | // 最後に使った奴を記憶 |
| gdc.s.para[GDC_WRITE] = ope; | setbiosgdc(csrw, &vect, 5, ope); |
| mem[MEMB_PRXDUPD] &= ~3; | |
| mem[MEMB_PRXDUPD] |= ope; | |
| } | } |
| Line 349 void bios0x18(void) { | Line 393 void bios0x18(void) { |
| BOOL b; | BOOL b; |
| UINT16 w; | UINT16 w; |
| UINT32 d; | UINT32 d; |
| const CRTDATA *crt; | |
| } tmp; | } tmp; |
| UINT pos; | UINT pos; |
| Line 420 const CRTDATA *crt; | Line 463 const CRTDATA *crt; |
| break; | break; |
| case 0x0a: // CRTモードの設定 | case 0x0a: // CRTモードの設定 |
| // GDCバッファを空に | bios0x18_0a(CPU_AL); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| gdc.mode1 &= ~(0x2d); | |
| mem[MEMB_CRT_STS_FLAG] = CPU_AL; | |
| tmp.crt = crtdata; | |
| if (!(np2cfg.dipsw[0] & 1)) { | |
| mem[MEMB_CRT_STS_FLAG] |= 0x80; | |
| gdc.mode1 |= 0x08; | |
| tmp.crt += 2; | |
| } | |
| if (CPU_AL & 0x01) { | |
| tmp.crt += 1; // 20行 | |
| } | |
| if (CPU_AL & 0x02) { | |
| gdc.mode1 |= 0x04; // 40桁 | |
| } | |
| if (CPU_AL & 0x04) { | |
| gdc.mode1 |= 0x01; // アトリビュート | |
| } | |
| if (CPU_AL & 0x08) { | |
| gdc.mode1 |= 0x20; // コードアクセス | |
| } | |
| mem[MEMB_CRT_RASTER] = tmp.crt->raster; | |
| crtc.reg.pl = tmp.crt->pl; | |
| crtc.reg.bl = tmp.crt->bl; | |
| crtc.reg.cl = tmp.crt->cl; | |
| crtc.reg.ssl = 0; | |
| gdc_restorekacmode(); | |
| bios0x18_10(0); | |
| break; | break; |
| case 0x0b: // CRTモードのセンス | case 0x0b: // CRTモードのセンス |
| Line 495 const CRTDATA *crt; | Line 506 const CRTDATA *crt; |
| break; | break; |
| case 0x0f: // 複数の表示領域の設定 | case 0x0f: // 複数の表示領域の設定 |
| // GDCバッファを空に | |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| SETBIOSMEM16(0x0053e, CPU_CX); | SETBIOSMEM16(0x0053e, CPU_CX); |
| SETBIOSMEM16(0x00540, CPU_BX); | SETBIOSMEM16(0x00540, CPU_BX); |
| mem[0x00547] = CPU_DH; | mem[0x00547] = CPU_DH; |
| Line 533 const CRTDATA *crt; | Line 550 const CRTDATA *crt; |
| gdc_work(GDCWORK_MASTER); | gdc_work(GDCWORK_MASTER); |
| } | } |
| gdc_forceready(&gdc.m); | gdc_forceready(&gdc.m); |
| bios0x18_10((REG8)(CPU_AL & 1)); | bios0x18_10((REG8)(CPU_AL & 1)); |
| break; | break; |
| Line 542 const CRTDATA *crt; | Line 560 const CRTDATA *crt; |
| gdc_work(GDCWORK_MASTER); | gdc_work(GDCWORK_MASTER); |
| } | } |
| gdc_forceready(&gdc.m); | gdc_forceready(&gdc.m); |
| // 00/08/02 | |
| if (gdc.m.para[GDC_CSRFORM] != (mem[MEMB_CRT_RASTER] | 0x80)) { | if (gdc.m.para[GDC_CSRFORM] != (mem[MEMB_CRT_RASTER] | 0x80)) { |
| gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER] | 0x80; | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER] | 0x80; |
| } | } |
| Line 555 const CRTDATA *crt; | Line 573 const CRTDATA *crt; |
| gdc_work(GDCWORK_MASTER); | gdc_work(GDCWORK_MASTER); |
| } | } |
| gdc_forceready(&gdc.m); | gdc_forceready(&gdc.m); |
| // 00/08/02 | |
| if (gdc.m.para[GDC_CSRFORM] != mem[MEMB_CRT_RASTER]) { | if (gdc.m.para[GDC_CSRFORM] != mem[MEMB_CRT_RASTER]) { |
| gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER]; | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER]; |
| gdcs.textdisp |= GDCSCRN_ALLDRAW | GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_ALLDRAW | GDCSCRN_EXT; |
| Line 771 const CRTDATA *crt; | Line 789 const CRTDATA *crt; |
| } | } |
| } | } |
| break; | break; |
| } | } |
| } | } |