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| version 1.13, 2004/02/09 20:39:39 | version 1.24, 2004/02/21 17:52:04 |
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| Line 2 | Line 2 |
| #include "cpucore.h" | #include "cpucore.h" |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| #include "gdc_sub.h" | |
| #include "bios.h" | #include "bios.h" |
| #include "biosmem.h" | #include "biosmem.h" |
| #include "font.h" | #include "font.h" |
| Line 52 static const CSRFORM csrform[4] = { | Line 53 static const CSRFORM csrform[4] = { |
| {0x07, 0x3b}, {0x09, 0x4b}, | {0x07, 0x3b}, {0x09, 0x4b}, |
| {0x0f, 0x7b}, {0x13, 0x9b}}; | {0x0f, 0x7b}, {0x13, 0x9b}}; |
| static const UINT8 sync200l[8] = {0x02,0x26,0x03,0x11,0x86,0x0f,0xc8,0x84}; | static const UINT8 sync200l[8] = {0x02,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94}; |
| static const UINT8 sync200m[8] = {0x02,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; | static const UINT8 sync200m[8] = {0x02,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; |
| static const UINT8 sync400m[8] = {0x02,0x4e,0x07,0x25,0x87,0x07,0x90,0x65}; | static const UINT8 sync400m[8] = {0x02,0x4e,0x07,0x25,0x87,0x07,0x90,0x65}; |
| Line 93 static void bios0x18_10(REG8 curdel) { | Line 94 static void bios0x18_10(REG8 curdel) { |
| gdcs.textdisp |= GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; |
| } | } |
| void bios0x18_16(BYTE chr, BYTE atr) { | void bios0x18_0a(REG8 mode) { |
| const CRTDATA *crt; | |
| gdc_forceready(GDCWORK_MASTER); | |
| gdc.mode1 &= ~(0x2d); | |
| mem[MEMB_CRT_STS_FLAG] = mode; | |
| crt = crtdata; | |
| if (!(np2cfg.dipsw[0] & 1)) { | |
| mem[MEMB_CRT_STS_FLAG] |= 0x80; | |
| gdc.mode1 |= 0x08; | |
| crt += 2; | |
| } | |
| if (mode & 0x01) { | |
| crt += 1; // 20行 | |
| } | |
| if (mode & 0x02) { | |
| gdc.mode1 |= 0x04; // 40桁 | |
| } | |
| if (mode & 0x04) { | |
| gdc.mode1 |= 0x01; // アトリビュート | |
| } | |
| if (mode & 0x08) { | |
| gdc.mode1 |= 0x20; // コードアクセス | |
| } | |
| mem[MEMB_CRT_RASTER] = crt->raster; | |
| crtc.reg.pl = crt->pl; | |
| crtc.reg.bl = crt->bl; | |
| crtc.reg.cl = crt->cl; | |
| crtc.reg.ssl = 0; | |
| gdc_restorekacmode(); | |
| bios0x18_10(0); | |
| } | |
| REG16 bios0x18_14(REG16 seg, REG16 off, REG16 code) { | |
| UINT16 size; | |
| const BYTE *p; | |
| BYTE buf[32]; | |
| UINT i; | |
| switch(code >> 8) { | |
| case 0x00: // 8x8 | |
| size = 0x0101; | |
| i286_memword_write(seg, off, 0x0101); | |
| p = fontrom + 0x82000 + ((code & 0xff) << 4); | |
| i286_memstr_write(seg, off + 2, p, 8); | |
| break; | |
| case 0x28: // 8x16 KANJI | |
| case 0x29: | |
| case 0x2a: | |
| case 0x2b: | |
| size = 0x0102; | |
| i286_memword_write(seg, off, 0x0102); | |
| p = fontrom; | |
| p += (code & 0x7f) << 12; | |
| p += (((code >> 8) - 0x20) & 0x7f) << 4; | |
| i286_memstr_write(seg, off + 2, p, 16); | |
| break; | |
| case 0x80: // 8x16 ANK | |
| size = 0x0102; | |
| p = fontrom + 0x80000 + ((code & 0xff) << 4); | |
| i286_memstr_write(seg, off + 2, p, 16); | |
| break; | |
| default: | |
| size = 0x0202; | |
| p = fontrom; | |
| p += (code & 0x7f) << 12; | |
| p += (((code >> 8) - 0x20) & 0x7f) << 4; | |
| for (i=0; i<16; i++, p++) { | |
| buf[i*2+0] = *p; | |
| buf[i*2+1] = *(p+0x800); | |
| } | |
| i286_memstr_write(seg, off + 2, buf, 32); | |
| break; | |
| } | |
| i286_memword_write(seg, off, size); | |
| return(size); | |
| } | |
| static void bios0x18_1a(REG16 seg, REG16 off, REG16 code) { | |
| BYTE *p; | |
| BYTE buf[32]; | |
| UINT i; | |
| if (((code >> 8) & 0x7e) == 0x76) { | |
| i286_memstr_read(seg, off + 2, buf, 32); | |
| p = fontrom; | |
| p += (code & 0x7f) << 12; | |
| p += (((code >> 8) - 0x20) & 0x7f) << 4; | |
| for (i=0; i<16; i++, p++) { | |
| *p = buf[i*2+0]; | |
| *(p+0x800) = buf[i*2+1]; | |
| } | |
| cgwindow.writable |= 0x80; | |
| } | |
| } | |
| void bios0x18_16(REG8 chr, REG8 atr) { | |
| UINT32 i; | UINT32 i; |
| Line 107 void bios0x18_16(BYTE chr, BYTE atr) { | Line 211 void bios0x18_16(BYTE chr, BYTE atr) { |
| gdcs.textdisp |= GDCSCRN_ALLDRAW; | gdcs.textdisp |= GDCSCRN_ALLDRAW; |
| } | } |
| #define SWAPU16(a, b) { UINT16 tmp; tmp = (a); (a) = (b); (b) = tmp; } | void bios0x18_40(void) { |
| gdc_forceready(GDCWORK_SLAVE); | |
| if (!(gdcs.grphdisp & GDCSCRN_ENABLE)) { | |
| gdcs.grphdisp |= GDCSCRN_ENABLE; | |
| screenupdate |= 2; | |
| } | |
| mem[MEMB_PRXCRT] |= 0x80; | |
| } | |
| void bios0x18_41(void) { | |
| gdc_forceready(GDCWORK_SLAVE); | |
| if (gdcs.grphdisp & GDCSCRN_ENABLE) { | |
| gdcs.grphdisp &= ~(GDCSCRN_ENABLE); | |
| screenupdate |= 2; | |
| } | |
| mem[MEMB_PRXCRT] &= 0x7f; | |
| } | |
| static REG8 swapbit(REG8 bit) { | void bios0x18_42(REG8 mode) { |
| REG8 ret; | BOOL b; |
| ret = 0; | gdc_forceready(GDCWORK_SLAVE); |
| while(bit) { | ZeroMemory(&gdc.s.para[GDC_SCROLL], 8); |
| ret = (ret << 1) + (bit & 1); | if ((mode & 0xc0) == 0xc0) { // ALL |
| bit >>= 1; | b = FALSE; |
| if ((mem[MEMB_PRXDUPD] & 0x24) == 0x20) { | |
| mem[MEMB_PRXDUPD] ^= 4; | |
| gdc.clock |= 3; | |
| CopyMemory(gdc.s.para + GDC_SYNC, sync400m, 8); | |
| gdc.s.para[GDC_PITCH] = 80; | |
| gdcs.grphdisp |= GDCSCRN_EXT; | |
| mem[MEMB_PRXDUPD] |= 0x08; | |
| } | |
| } | |
| else { | |
| b = TRUE; | |
| if ((mem[MEMB_PRXDUPD] & 0x24) == 0x24) { | |
| mem[MEMB_PRXDUPD] ^= 4; | |
| gdc.clock &= ~3; | |
| CopyMemory(gdc.s.para + GDC_SYNC, | |
| (mem[MEMB_PRXCRT] & 0x40)?sync200m:sync200l, 8); | |
| gdc.s.para[GDC_PITCH] = 40; | |
| gdcs.grphdisp |= GDCSCRN_EXT; | |
| mem[MEMB_PRXDUPD] |= 0x08; | |
| } | |
| if (mode & 0x40) { // UPPER | |
| gdc.s.para[GDC_SCROLL+0] = (200*40) & 0xff; | |
| gdc.s.para[GDC_SCROLL+1] = (200*40) >> 8; | |
| } | |
| } | } |
| return(ret); | if ((!b) || (!(mem[MEMB_PRXCRT] & 0x40))) { |
| gdc.mode1 &= ~(0x10); | |
| gdc.s.para[GDC_CSRFORM] = 0; | |
| } | |
| else { | |
| gdc.mode1 |= 0x10; | |
| gdc.s.para[GDC_CSRFORM] = 1; | |
| } | |
| gdcs.disp = (mode >> 4) & 1; | |
| if (!(mode & 0x20)) { | |
| gdc.mode1 &= ~0x04; | |
| } | |
| else { | |
| gdc.mode2 |= 0x04; | |
| } | |
| gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | |
| screenupdate |= 2; | |
| } | |
| static void setbiosgdc(UINT32 csrw, const GDCVECT *vect, UINT8 ope) { | |
| gdc.s.para[GDC_CSRW + 0] = (BYTE)csrw; | |
| gdc.s.para[GDC_CSRW + 1] = (BYTE)(csrw >> 8); | |
| gdc.s.para[GDC_CSRW + 2] = (BYTE)(csrw >> 16); | |
| gdc.s.para[GDC_VECTW] = vect->ope; | |
| gdc_vectreset(&gdc.s); | |
| gdc.s.para[GDC_WRITE] = ope; | |
| mem[MEMB_PRXDUPD] &= ~3; | |
| mem[MEMB_PRXDUPD] |= ope; | |
| } | } |
| static void bios18_47(void) { | |
| static void bios0x18_47(void) { | |
| UCWTBL ucw; | UCWTBL ucw; |
| GDCVECT vect; | GDCVECT vect; |
| Line 132 static void bios18_47(void) { | Line 309 static void bios18_47(void) { |
| GDCSUBFN func; | GDCSUBFN func; |
| UINT32 csrw; | UINT32 csrw; |
| UINT16 data; | UINT16 data; |
| UINT16 data2; | |
| UINT16 GBMDOTI; | UINT16 GBMDOTI; |
| UINT8 ope; | UINT8 ope; |
| SINT16 dx; | |
| SINT16 dy; | |
| // GDCバッファを空に | gdc_forceready(GDCWORK_SLAVE); |
| if (gdc.s.cnt) { | |
| gdc_work(GDCWORK_SLAVE); | |
| } | |
| gdc_forceready(&gdc.s); | |
| i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); |
| GBSX1 = LOADINTELWORD(ucw.GBSX1); | GBSX1 = LOADINTELWORD(ucw.GBSX1); |
| GBSY1 = LOADINTELWORD(ucw.GBSY1); | GBSY1 = LOADINTELWORD(ucw.GBSY1); |
| GBSX2 = LOADINTELWORD(ucw.GBSX2); | GBSX2 = LOADINTELWORD(ucw.GBSX2); |
| GBSY2 = LOADINTELWORD(ucw.GBSY2); | GBSY2 = LOADINTELWORD(ucw.GBSY2); |
| ZeroMemory(&vect, sizeof(vect)); | ZeroMemory(&vect, sizeof(vect)); |
| data = 0; | |
| data2 = 0; | |
| if (ucw.GBDTYP == 0x01) { | if (ucw.GBDTYP == 0x01) { |
| short dx, dy; | func = gdcsub_vectl; |
| func = gdcsub_line; | gdcsub_setvectl(&vect, GBSX1, GBSY1, GBSX2, GBSY2); |
| if ((GBSX1 > GBSX2) || | } |
| ((GBSX1 == GBSX2) && (GBSY1 > GBSY2))) { | else if (ucw.GBDTYP <= 0x02) { |
| SWAPU16(GBSX1, GBSX2); | func = gdcsub_vectr; |
| SWAPU16(GBSY1, GBSY2); | vect.ope = 0x40 + (ucw.GBDSP & 7); |
| } | |
| dx = GBSX2 - GBSX1; | dx = GBSX2 - GBSX1; |
| dy = GBSY2 - GBSY1; | if (dx < 0) { |
| if (dy > 0) { | dx = 0 - dx; |
| if (dx < dy) { | |
| vect.ope = 0; | |
| SWAPU16(dx, dy); | |
| } | |
| else { | |
| vect.ope = 1; | |
| } | |
| } | } |
| else { | dy = GBSY2 - GBSY1; |
| dy = -dy; | if (dy < 0) { |
| if (dx > dy) { | dy = 0 - dy; |
| vect.ope = 2; | |
| } | |
| else { | |
| vect.ope = 3; | |
| SWAPU16(dx, dy); | |
| } | |
| } | |
| STOREINTELWORD(vect.DC, dx); | |
| data = dy * 2; | |
| STOREINTELWORD(vect.D1, data); | |
| data -= dx; | |
| STOREINTELWORD(vect.D, data); | |
| data -= dx; | |
| STOREINTELWORD(vect.D2, data); | |
| } | |
| else if (ucw.GBDTYP == 0x02) { | |
| func = gdcsub_box; | |
| if (GBSX1 > GBSX2) { | |
| SWAPU16(GBSX1, GBSX2); | |
| } | } |
| if (GBSY1 > GBSY2) { | switch(ucw.GBDSP & 3) { |
| SWAPU16(GBSY1, GBSY2); | case 0: |
| data = dy; | |
| data2 = dx; | |
| break; | |
| case 1: | |
| data2 = (UINT16)dx + (UINT16)dy; | |
| data2 >>= 1; | |
| data = (UINT16)dx - (UINT16)dy; | |
| data = (data >> 1) & 0x3fff; | |
| break; | |
| case 2: | |
| data = dx; | |
| data2 = dy; | |
| break; | |
| case 3: | |
| data2 = (UINT16)dx + (UINT16)dy; | |
| data2 >>= 1; | |
| data = (UINT16)dy - (UINT16)dx; | |
| data = (data >> 1) & 0x3fff; | |
| break; | |
| } | } |
| STOREINTELWORD(vect.DC, 3); | STOREINTELWORD(vect.DC, 3); |
| STOREINTELWORD(vect.D, data); | |
| STOREINTELWORD(vect.D2, data2); | |
| STOREINTELWORD(vect.D1, 0xffff); | STOREINTELWORD(vect.D1, 0xffff); |
| data = GBSX2 - GBSX1; | |
| STOREINTELWORD(vect.DM, data); | STOREINTELWORD(vect.DM, data); |
| STOREINTELWORD(vect.D2, data); | |
| data = GBSY2 - GBSY1; | |
| STOREINTELWORD(vect.D, data); | |
| } | } |
| else { | else { |
| func = gdcsub_null; | func = gdcsub_vectc; |
| vect.ope = 0x20 + (ucw.GBDSP & 7); | |
| vect.DC[0] = ucw.GBLNG1[0]; | |
| vect.DC[1] = ucw.GBLNG1[1]; | |
| data = LOADINTELWORD(ucw.GBLNG2) - 1; | |
| STOREINTELWORD(vect.D, data); | |
| data >>= 1; | |
| STOREINTELWORD(vect.D2, data); | |
| STOREINTELWORD(vect.D1, 0x3fff); | |
| if (ucw.GBDTYP == 0x04) { | |
| vect.DM[0] = ucw.GBMDOT[0]; | |
| vect.DM[1] = ucw.GBMDOT[1]; | |
| } | |
| } | } |
| if ((CPU_CH & 0xc0) == 0x40) { | if ((CPU_CH & 0xc0) == 0x40) { |
| GBSY1 += 200; | GBSY1 += 200; |
| } | } |
| csrw = (GBSY1 * 40) + (GBSX1 >> 4); | csrw = (GBSY1 * 40) + (GBSX1 >> 4); |
| csrw += (GBSX1 & 0xf) << 20; | csrw += (GBSX1 & 0xf) << 20; |
| GBMDOTI = (swapbit(ucw.GBMDOTI[0]) << 8) + swapbit(ucw.GBMDOTI[1]); | GBMDOTI = (GDCPATREVERSE(ucw.GBMDOTI[0]) << 8) + |
| GDCPATREVERSE(ucw.GBMDOTI[1]); | |
| if ((CPU_CH & 0x30) == 0x30) { | if ((CPU_CH & 0x30) == 0x30) { |
| ope = (ucw.GBON_PTN & 1)?GDCOPE_SET:GDCOPE_CLEAR; | ope = (ucw.GBON_PTN & 1)?GDCOPE_SET:GDCOPE_CLEAR; |
| func(csrw + 0x4000, &vect, GBMDOTI, ope); | func(csrw + 0x4000, &vect, GBMDOTI, ope); |
| Line 227 static void bios18_47(void) { | Line 409 static void bios18_47(void) { |
| // 最後に使った奴を記憶 | // 最後に使った奴を記憶 |
| *(UINT16 *)(mem + MEMW_PRXGLS) = *(UINT16 *)(ucw.GBMDOTI); | *(UINT16 *)(mem + MEMW_PRXGLS) = *(UINT16 *)(ucw.GBMDOTI); |
| *(UINT16 *)(gdc.s.para + GDC_TEXTW) = *(UINT16 *)(ucw.GBMDOTI); | STOREINTELWORD(mem + GDC_TEXTW, GBMDOTI); |
| setbiosgdc(csrw, &vect, ope); | |
| gdc.s.para[GDC_WRITE] = ope; | |
| mem[MEMB_PRXDUPD] &= ~3; | |
| mem[MEMB_PRXDUPD] |= ope; | |
| } | } |
| static void bios18_49(void) { | static void bios0x18_49(void) { |
| UCWTBL ucw; | UCWTBL ucw; |
| UINT i; | UINT i; |
| Line 246 static void bios18_49(void) { | Line 425 static void bios18_49(void) { |
| UINT32 csrw; | UINT32 csrw; |
| UINT8 ope; | UINT8 ope; |
| // GDCバッファを空に | gdc_forceready(GDCWORK_SLAVE); |
| if (gdc.s.cnt) { | |
| gdc_work(GDCWORK_SLAVE); | |
| } | |
| gdc_forceready(&gdc.s); | |
| i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); | i286_memstr_read(CPU_DS, CPU_BX, &ucw, sizeof(ucw)); |
| for (i=0; i<8; i++) { | for (i=0; i<8; i++) { |
| mem[MEMW_PRXGLS + i] = ucw.GBMDOTI[i]; | mem[MEMW_PRXGLS + i] = ucw.GBMDOTI[i]; |
| pat[i] = swapbit(ucw.GBMDOTI[i]); | pat[i] = GDCPATREVERSE(ucw.GBMDOTI[i]); |
| gdc.s.para[GDC_TEXTW + i] = pat[i]; | gdc.s.para[GDC_TEXTW + i] = pat[i]; |
| } | } |
| vect.ope = 0x10 + (ucw.GBDSP & 7); | vect.ope = 0x10 + (ucw.GBDSP & 7); |
| Line 267 static void bios18_49(void) { | Line 442 static void bios18_49(void) { |
| } | } |
| else { | else { |
| STOREINTELWORD(vect.DC, 7); | STOREINTELWORD(vect.DC, 7); |
| vect.D[0] = gdc.s.para[GDC_VECTW + 3]; | STOREINTELWORD(vect.D, 7); |
| vect.D[1] = gdc.s.para[GDC_VECTW + 4]; | |
| } | } |
| GBSX1 = LOADINTELWORD(ucw.GBSX1); | GBSX1 = LOADINTELWORD(ucw.GBSX1); |
| Line 294 static void bios18_49(void) { | Line 468 static void bios18_49(void) { |
| } | } |
| // 最後に使った奴を記憶 | // 最後に使った奴を記憶 |
| gdc.s.para[GDC_WRITE] = ope; | setbiosgdc(csrw, &vect, ope); |
| mem[MEMB_PRXDUPD] &= ~3; | |
| mem[MEMB_PRXDUPD] |= ope; | |
| } | } |
| Line 308 void bios0x18(void) { | Line 480 void bios0x18(void) { |
| BOOL b; | BOOL b; |
| UINT16 w; | UINT16 w; |
| UINT32 d; | UINT32 d; |
| const CRTDATA *crt; | UINT8 col[4]; |
| } tmp; | } tmp; |
| UINT pos; | UINT pos; |
| BYTE buf[34]; | |
| BYTE *p; | BYTE *p; |
| int i; | int i; |
| Line 379 const CRTDATA *crt; | Line 550 const CRTDATA *crt; |
| break; | break; |
| case 0x0a: // CRTモードの設定 | case 0x0a: // CRTモードの設定 |
| // GDCバッファを空に | bios0x18_0a(CPU_AL); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| gdc.mode1 &= ~(0x2d); | |
| mem[MEMB_CRT_STS_FLAG] = CPU_AL; | |
| tmp.crt = crtdata; | |
| if (!(np2cfg.dipsw[0] & 1)) { | |
| mem[MEMB_CRT_STS_FLAG] |= 0x80; | |
| gdc.mode1 |= 0x08; | |
| tmp.crt += 2; | |
| } | |
| if (CPU_AL & 0x01) { | |
| tmp.crt += 1; // 20行 | |
| } | |
| if (CPU_AL & 0x02) { | |
| gdc.mode1 |= 0x04; // 40桁 | |
| } | |
| if (CPU_AL & 0x04) { | |
| gdc.mode1 |= 0x01; // アトリビュート | |
| } | |
| if (CPU_AL & 0x08) { | |
| gdc.mode1 |= 0x20; // コードアクセス | |
| } | |
| mem[MEMB_CRT_RASTER] = tmp.crt->raster; | |
| crtc.reg.pl = tmp.crt->pl; | |
| crtc.reg.bl = tmp.crt->bl; | |
| crtc.reg.cl = tmp.crt->cl; | |
| crtc.reg.ssl = 0; | |
| gdc_restorekacmode(); | |
| bios0x18_10(0); | |
| break; | break; |
| case 0x0b: // CRTモードのセンス | case 0x0b: // CRTモードのセンス |
| Line 433 const CRTDATA *crt; | Line 572 const CRTDATA *crt; |
| break; | break; |
| case 0x0e: // 一つの表示領域の設定 | case 0x0e: // 一つの表示領域の設定 |
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| ZeroMemory(&gdc.m.para[GDC_SCROLL], 16); | ZeroMemory(&gdc.m.para[GDC_SCROLL], 16); |
| tmp.w = CPU_DX >> 1; | tmp.w = CPU_DX >> 1; |
| Line 454 const CRTDATA *crt; | Line 589 const CRTDATA *crt; |
| break; | break; |
| case 0x0f: // 複数の表示領域の設定 | case 0x0f: // 複数の表示領域の設定 |
| gdc_forceready(GDCWORK_MASTER); | |
| SETBIOSMEM16(0x0053e, CPU_CX); | SETBIOSMEM16(0x0053e, CPU_CX); |
| SETBIOSMEM16(0x00540, CPU_BX); | SETBIOSMEM16(0x00540, CPU_BX); |
| mem[0x00547] = CPU_DH; | mem[0x00547] = CPU_DH; |
| Line 487 const CRTDATA *crt; | Line 624 const CRTDATA *crt; |
| break; | break; |
| case 0x10: // カーソルタイプの設定 | case 0x10: // カーソルタイプの設定 |
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| bios0x18_10((REG8)(CPU_AL & 1)); | bios0x18_10((REG8)(CPU_AL & 1)); |
| break; | break; |
| case 0x11: // カーソルの表示開始 | case 0x11: // カーソルの表示開始 |
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| // 00/08/02 | |
| if (gdc.m.para[GDC_CSRFORM] != (mem[MEMB_CRT_RASTER] | 0x80)) { | if (gdc.m.para[GDC_CSRFORM] != (mem[MEMB_CRT_RASTER] | 0x80)) { |
| gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER] | 0x80; | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER] | 0x80; |
| } | } |
| Line 509 const CRTDATA *crt; | Line 639 const CRTDATA *crt; |
| break; | break; |
| case 0x12: // カーソルの表示停止 | case 0x12: // カーソルの表示停止 |
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| // 00/08/02 | |
| if (gdc.m.para[GDC_CSRFORM] != mem[MEMB_CRT_RASTER]) { | if (gdc.m.para[GDC_CSRFORM] != mem[MEMB_CRT_RASTER]) { |
| gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER]; | gdc.m.para[GDC_CSRFORM] = mem[MEMB_CRT_RASTER]; |
| gdcs.textdisp |= GDCSCRN_ALLDRAW | GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_ALLDRAW | GDCSCRN_EXT; |
| Line 522 const CRTDATA *crt; | Line 648 const CRTDATA *crt; |
| break; | break; |
| case 0x13: // カーソル位置の設定 | case 0x13: // カーソル位置の設定 |
| // GDCバッファを空に | gdc_forceready(GDCWORK_MASTER); |
| if (gdc.m.cnt) { | |
| gdc_work(GDCWORK_MASTER); | |
| } | |
| gdc_forceready(&gdc.m); | |
| tmp.w = CPU_DX >> 1; | tmp.w = CPU_DX >> 1; |
| if (LOADINTELWORD(gdc.m.para + GDC_CSRW) != tmp.w) { | if (LOADINTELWORD(gdc.m.para + GDC_CSRW) != tmp.w) { |
| Line 536 const CRTDATA *crt; | Line 658 const CRTDATA *crt; |
| break; | break; |
| case 0x14: // フォントパターンの読み出し | case 0x14: // フォントパターンの読み出し |
| switch(CPU_DH) { | bios0x18_14(CPU_BX, CPU_CX, CPU_DX); |
| case 0x00: // 8x8 | |
| i286_memword_write(CPU_BX, CPU_CX, 0x0101); | |
| i286_memstr_write(CPU_BX, CPU_CX + 2, | |
| fontrom + 0x82000 + (CPU_DL << 4), 8); | |
| break; | |
| case 0x28: // 8x16 KANJI | |
| case 0x29: | |
| case 0x2a: | |
| case 0x2b: | |
| i286_memword_write(CPU_BX, CPU_CX, 0x0102); | |
| i286_memstr_write(CPU_BX, CPU_CX + 2, | |
| fontrom + ((CPU_DL & 0x7f) << 12) | |
| + ((CPU_DH - 0x20) << 4), 16); | |
| break; | |
| case 0x80: // 8x16 ANK | |
| i286_memword_write(CPU_BX, CPU_CX, 0x0102); | |
| i286_memstr_write(CPU_BX, CPU_CX + 2, | |
| fontrom + 0x80000 + (CPU_DL << 4), 16); | |
| break; | |
| default: | |
| buf[0] = 0x02; | |
| buf[1] = 0x02; | |
| p = fontrom + ((CPU_DL & 0x7f) << 12) | |
| + (((CPU_DH - 0x20) & 0x7f) << 4); | |
| for (i=1; i<17; i++, p++) { | |
| buf[i*2+0] = *p; | |
| buf[i*2+1] = *(p+0x800); | |
| } | |
| i286_memstr_write(CPU_BX, CPU_CX, buf, 34); | |
| break; | |
| } | |
| break; | break; |
| case 0x15: // ライトペン位置読みだし | case 0x15: // ライトペン位置読みだし |
| Line 592 const CRTDATA *crt; | Line 680 const CRTDATA *crt; |
| break; | break; |
| case 0x1a: // ユーザー文字の定義 | case 0x1a: // ユーザー文字の定義 |
| if ((CPU_DH & 0x7e) == 0x76) { | bios0x18_1a(CPU_BX, CPU_CX, CPU_DX); |
| i286_memstr_read(CPU_BX, CPU_CX + 2, buf, 32); | |
| p = fontrom + ((CPU_DL & 0x7f) << 12) | |
| + (((CPU_DH - 0x20) & 0x7f) << 4); | |
| for (i=0; i<16; i++, p++) { | |
| *p = buf[i*2+0]; | |
| *(p+0x800) = buf[i*2+1]; | |
| } | |
| cgwindow.writable |= 0x80; | |
| } | |
| break; | break; |
| case 0x1b: // KCGアクセスモードの設定 | case 0x1b: // KCGアクセスモードの設定 |
| Line 621 const CRTDATA *crt; | Line 700 const CRTDATA *crt; |
| break; | break; |
| case 0x40: // グラフィック画面の表示開始 | case 0x40: // グラフィック画面の表示開始 |
| // GDCバッファを空に | bios0x18_40(); |
| if (gdc.s.cnt) { | |
| gdc_work(GDCWORK_SLAVE); | |
| } | |
| if (!(gdcs.grphdisp & GDCSCRN_ENABLE)) { | |
| gdcs.grphdisp |= GDCSCRN_ENABLE; | |
| screenupdate |= 2; | |
| } | |
| mem[MEMB_PRXCRT] |= 0x80; | |
| break; | break; |
| case 0x41: // グラフィック画面の表示終了 | case 0x41: // グラフィック画面の表示終了 |
| // GDCバッファを空に | bios0x18_41(); |
| if (gdc.s.cnt) { | |
| gdc_work(GDCWORK_SLAVE); | |
| } | |
| gdc_forceready(&gdc.s); | |
| if (gdcs.grphdisp & GDCSCRN_ENABLE) { | |
| gdcs.grphdisp &= ~(GDCSCRN_ENABLE); | |
| screenupdate |= 2; | |
| } | |
| mem[MEMB_PRXCRT] &= 0x7f; | |
| break; | break; |
| case 0x42: // 表示領域の設定 | case 0x42: // 表示領域の設定 |
| // GDCバッファを空に | bios0x18_42(CPU_CH); |
| if (gdc.s.cnt) { | |
| gdc_work(GDCWORK_SLAVE); | |
| } | |
| gdc_forceready(&gdc.s); | |
| ZeroMemory(&gdc.s.para[GDC_SCROLL], 8); | |
| if ((CPU_CH & 0xc0) == 0xc0) { // ALL | |
| tmp.b = FALSE; | |
| if ((mem[MEMB_PRXDUPD] & 0x24) == 0x20) { | |
| mem[MEMB_PRXDUPD] ^= 4; | |
| gdc.clock |= 3; | |
| CopyMemory(gdc.s.para + GDC_SYNC, sync400m, 8); | |
| gdc.s.para[GDC_PITCH] = 80; | |
| gdcs.grphdisp |= GDCSCRN_EXT; | |
| mem[MEMB_PRXDUPD] |= 0x08; | |
| } | |
| } | |
| else { | |
| tmp.b = TRUE; | |
| if ((mem[MEMB_PRXDUPD] & 0x24) == 0x24) { | |
| mem[MEMB_PRXDUPD] ^= 4; | |
| gdc.clock &= ~3; | |
| CopyMemory(gdc.s.para + GDC_SYNC, | |
| (mem[MEMB_PRXCRT] & 0x40)?sync200m:sync200l, 8); | |
| gdc.s.para[GDC_PITCH] = 40; | |
| gdcs.grphdisp |= GDCSCRN_EXT; | |
| mem[MEMB_PRXDUPD] |= 0x08; | |
| } | |
| if (CPU_CH & 0x40) { // UPPER | |
| gdc.s.para[GDC_SCROLL+0] = (200*40) & 0xff; | |
| gdc.s.para[GDC_SCROLL+1] = (200*40) >> 8; | |
| } | |
| } | |
| if ((!tmp.b) || (!(mem[MEMB_PRXCRT] & 0x40))) { | |
| gdc.mode1 &= ~(0x10); | |
| gdc.s.para[GDC_CSRFORM] = 0; | |
| } | |
| else { | |
| gdc.mode1 |= 0x10; | |
| gdc.s.para[GDC_CSRFORM] = 1; | |
| } | |
| gdcs.disp = (CPU_CH >> 4) & 1; | |
| gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | |
| screenupdate |= 2; | |
| break; | break; |
| case 0x43: // パレットの設定 | case 0x43: // パレットの設定 |
| i286_memstr_read(CPU_DS, CPU_BX + offsetof(UCWTBL, GBCPC), | i286_memstr_read(CPU_DS, CPU_BX + offsetof(UCWTBL, GBCPC), |
| buf, 4); | tmp.col, 4); |
| tmp.d = LOADINTELDWORD(buf); | for (i=0; i<4; i++) { |
| for (i=8; i--;) { | gdc_setdegitalpal(6 - (i*2), (REG8)(tmp.col[i] >> 4)); |
| gdc_setdegitalpal(i, (REG8)(tmp.d & 15)); | gdc_setdegitalpal(7 - (i*2), (REG8)(tmp.col[i] & 15)); |
| tmp.d >>= 4; | |
| } | } |
| break; | break; |
| case 0x44: // ボーダカラー | case 0x44: // ボーダカラーの設定 |
| // if (!(mem[MEMB_PRXCRT] & 0x40)) { | // if (!(mem[MEMB_PRXCRT] & 0x40)) { |
| // color = i286_membyte_read(CPU_DS, CPU_BX + 1); | // color = i286_membyte_read(CPU_DS, CPU_BX + 1); |
| // } | // } |
| break; | break; |
| case 0x45: | |
| case 0x46: | |
| TRACEOUT(("unsupport bios 18-%.2x", CPU_AH)); | |
| break; | |
| case 0x47: // 直線、矩形の描画 | case 0x47: // 直線、矩形の描画 |
| case 0x48: | case 0x48: // 円の描画 |
| bios18_47(); | bios0x18_47(); |
| break; | break; |
| case 0x49: // | case 0x49: // グラフィック文字の描画 |
| bios18_49(); | bios0x18_49(); |
| break; | break; |
| case 0x4a: // | case 0x4a: // 描画モードの設定 |
| if (!(mem[MEMB_PRXCRT] & 0x01)) { | if (!(mem[MEMB_PRXCRT] & 0x01)) { |
| gdc.s.para[GDC_SYNC] = CPU_CH; | gdc.s.para[GDC_SYNC] = CPU_CH; |
| gdcs.grphdisp |= GDCSCRN_EXT; | gdcs.grphdisp |= GDCSCRN_EXT; |
| Line 730 const CRTDATA *crt; | Line 752 const CRTDATA *crt; |
| } | } |
| } | } |
| break; | break; |
| } | } |
| } | } |