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| version 1.34, 2004/04/06 18:41:00 | version 1.36, 2004/06/02 11:02:53 |
|---|---|
| Line 474 void bios0x18_42(REG8 mode) { | Line 474 void bios0x18_42(REG8 mode) { |
| scrn = bios0x18_31bh(); | scrn = bios0x18_31bh(); |
| if ((mem[MEMB_CRT_BIOS] & 0x80) && | if ((mem[MEMB_CRT_BIOS] & 0x80) && |
| (((scrn & 0x30) == 0x30) || (crtmode == 3))) { | (((scrn & 0x30) == 0x30) || (crtmode == 3))) { |
| bios0x18_30(rate, (crtmode << 4) + 1); | bios0x18_30(rate, (REG8)((crtmode << 4) + 1)); |
| } | } |
| else { | else { |
| #endif | #endif |
| Line 626 static void bios0x18_47(void) { | Line 626 static void bios0x18_47(void) { |
| vect.ope = 0x20 + (ucw.GBDSP & 7); | vect.ope = 0x20 + (ucw.GBDSP & 7); |
| vect.DC[0] = ucw.GBLNG1[0]; | vect.DC[0] = ucw.GBLNG1[0]; |
| vect.DC[1] = ucw.GBLNG1[1]; | vect.DC[1] = ucw.GBLNG1[1]; |
| data = LOADINTELWORD(ucw.GBLNG2) - 1; | // data = LOADINTELWORD(ucw.GBLNG2) - 1; |
| data = LOADINTELWORD(ucw.GBCIR) - 1; | |
| STOREINTELWORD(vect.D, data); | STOREINTELWORD(vect.D, data); |
| data >>= 1; | data >>= 1; |
| STOREINTELWORD(vect.D2, data); | STOREINTELWORD(vect.D2, data); |