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version 1.34, 2004/04/06 18:41:00
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version 1.37, 2004/06/03 16:20:52
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Line 219 const BYTE *p;
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Line 219 const BYTE *p;
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| MEML_WRITESTR(seg, off + 2, p, 8); |
MEML_WRITESTR(seg, off + 2, p, 8); |
| break; |
break; |
| |
|
| case 0x28: // 8x16 KANJI |
// case 0x28: |
| case 0x29: |
case 0x29: // 8x16 KANJI |
| case 0x2a: |
case 0x2a: |
| case 0x2b: |
case 0x2b: |
| size = 0x0102; |
size = 0x0102; |
|
Line 474 void bios0x18_42(REG8 mode) {
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Line 474 void bios0x18_42(REG8 mode) {
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| scrn = bios0x18_31bh(); |
scrn = bios0x18_31bh(); |
| if ((mem[MEMB_CRT_BIOS] & 0x80) && |
if ((mem[MEMB_CRT_BIOS] & 0x80) && |
| (((scrn & 0x30) == 0x30) || (crtmode == 3))) { |
(((scrn & 0x30) == 0x30) || (crtmode == 3))) { |
| bios0x18_30(rate, (crtmode << 4) + 1); |
bios0x18_30(rate, (REG8)((crtmode << 4) + 1)); |
| } |
} |
| else { |
else { |
| #endif |
#endif |
|
Line 626 static void bios0x18_47(void) {
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Line 626 static void bios0x18_47(void) {
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| vect.ope = 0x20 + (ucw.GBDSP & 7); |
vect.ope = 0x20 + (ucw.GBDSP & 7); |
| vect.DC[0] = ucw.GBLNG1[0]; |
vect.DC[0] = ucw.GBLNG1[0]; |
| vect.DC[1] = ucw.GBLNG1[1]; |
vect.DC[1] = ucw.GBLNG1[1]; |
| data = LOADINTELWORD(ucw.GBLNG2) - 1; |
// data = LOADINTELWORD(ucw.GBLNG2) - 1; |
| |
data = LOADINTELWORD(ucw.GBCIR) - 1; |
| STOREINTELWORD(vect.D, data); |
STOREINTELWORD(vect.D, data); |
| data >>= 1; |
data >>= 1; |
| STOREINTELWORD(vect.D2, data); |
STOREINTELWORD(vect.D2, data); |
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