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| version 1.40, 2005/02/07 14:46:07 | version 1.41, 2005/03/16 09:33:53 |
|---|---|
| Line 530 void bios0x18_42(REG8 mode) { | Line 530 void bios0x18_42(REG8 mode) { |
| gdcs.disp = (mode >> 4) & 1; | gdcs.disp = (mode >> 4) & 1; |
| } | } |
| if (!(mode & 0x20)) { | if (!(mode & 0x20)) { |
| gdc.mode1 &= ~0x04; | gdc.mode2 &= ~0x04; |
| } | } |
| else { | else { |
| gdc.mode2 |= 0x04; | gdc.mode2 |= 0x04; |
| } | } |
| gdcs.mode2 = gdc.mode2; | |
| gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | gdcs.grphdisp |= GDCSCRN_ALLDRAW2; |
| screenupdate |= 2; | screenupdate |= 2; |
| } | } |
| Line 765 void bios0x18(void) { | Line 766 void bios0x18(void) { |
| } tmp; | } tmp; |
| int i; | int i; |
| #if 0 | #if 1 |
| TRACEOUT(("int18 AX=%.4x %.4x:%.4x", CPU_AX, | TRACEOUT(("int18 AX=%.4x %.4x:%.4x", CPU_AX, |
| MEML_READ16(CPU_SS, CPU_SP+2), | MEML_READ16(CPU_SS, CPU_SP+2), |
| MEML_READ16(CPU_SS, CPU_SP))); | MEML_READ16(CPU_SS, CPU_SP))); |