--- np2/bios/bios18.c	2004/02/29 00:57:06	1.26
+++ np2/bios/bios18.c	2004/03/01 05:29:58	1.29
@@ -284,24 +284,35 @@ void bios0x18_16(REG8 chr, REG8 atr) {
 // ---- 31khz
 
 #if defined(SUPPORT_CRT31KHZ)
-static REG8 bios0x18_30(REG8 mode, REG8 scrn) {
+static REG8 bios0x18_30(REG8 rate, REG8 scrn) {
 
 	int			crt;
 	int			master;
 	int			slave;
 const CRTDATA	*p;
 
-	if (((mode & 0xf8) != 0x08) || (scrn & (~0x33)) || ((scrn & 3) == 3)) {
-		return(1);
+	if (((rate & 0xf8) != 0x08) || (scrn & (~0x33)) || ((scrn & 3) == 3)) {
+		return(0);
 	}
 	if ((scrn & 0x30) == 0x30) {				// 640x480
-		return(1);
+#if defined(SUPPORT_PC9821)
+		if (rate & 4) {
+			gdc_analogext(TRUE);
+			mem[MEMB_PRXDUPD] |= 0x80;
+			crt = 4;
+			master = 3;
+			slave = 1;
+			gdc.analog |= (1 << GDCANALOG_256E);
+		}
+		else
+#endif
+		return(0);
 	}
 	else {
 		if ((scrn & 3) >= 2) {
-			return(1);
+			return(0);
 		}
-		if (mode & 4) {							// 31khz
+		if (rate & 4) {							// 31khz
 			crt = 2;
 			master = 2;
 			slave = 4;
@@ -319,11 +330,18 @@ const CRTDATA	*p;
 		if ((scrn & 0x20) && (mem[MEMB_PRXDUPD] & 0x04)) {
 			slave += 1;
 		}
+#if defined(SUPPORT_PC9821)
+		else {
+			gdc_analogext(FALSE);
+			mem[MEMB_PRXDUPD] &= ~0x80;
+		}
+		gdc.analog &= ~(1 << (GDCANALOG_256E));
+#endif
 	}
 	crt += (scrn & 3);
 	master += (scrn & 3);
 
-	if (mode & 4) {
+	if (rate & 4) {
 		gdc.display |= (1 << GDCDISP_31);
 	}
 	else {
@@ -372,7 +390,6 @@ const CRTDATA	*p;
 
 	gdcs.textdisp &= ~GDCSCRN_ENABLE;
 	gdcs.textdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2;
-	gdcs.grphdisp &= ~GDCSCRN_ENABLE;
 	gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2;
 	screenupdate |= 2;
 
@@ -385,15 +402,15 @@ const CRTDATA	*p;
 	if (scrn & 2) {
 		mem[MEMB_CRT_STS_FLAG] |= 0x10;
 	}
-	return(0);
+	return(5);			// 最後にGDCへ送ったデータ…
 }
 
 static REG8 bios0x18_31al(void) {
 
-	UINT8	mode;
+	UINT8	rate;
 
-	mode = 0x08 + ((gdc.display >> (GDCDISP_31 - 5)) & 4);
-	return(mode);
+	rate = 0x08 + ((gdc.display >> (GDCDISP_31 - 5)) & 4);
+	return(rate);
 }
 
 static REG8 bios0x18_31bh(void) {
@@ -437,18 +454,24 @@ void bios0x18_41(void) {
 void bios0x18_42(REG8 mode) {
 
 	UINT8	crtmode;
+#if defined(SUPPORT_CRT31KHZ)
+	UINT8	rate;
+	UINT8	scrn;
+#endif
+	int		slave;
 
 	gdc_forceready(GDCWORK_MASTER);
 	gdc_forceready(GDCWORK_SLAVE);
 
 	crtmode = modenum[mode >> 6];
 #if defined(SUPPORT_CRT31KHZ)
-	if (mem[MEMB_CRT_BIOS] & 0x80) {
-		bios0x18_30(bios0x18_31al(), (crtmode << 4) + (bios0x18_31bh() & 3));
+	rate = bios0x18_31al();
+	scrn = bios0x18_31bh();
+	if ((mem[MEMB_CRT_BIOS] & 0x80) &&
+		(((scrn & 0x30) == 0x30) || (crtmode == 3))) {
+		bios0x18_30(rate, (crtmode << 4) + 1);
 	}
 	else {
-		mem[MEMB_CRT_BIOS] &= ~3;
-		mem[MEMB_CRT_BIOS] |= crtmode;
 #endif
 		ZeroMemory(gdc.s.para + GDC_SCROLL, 8);
 		if (crtmode == 2) {							// ALL
@@ -456,24 +479,27 @@ void bios0x18_42(REG8 mode) {
 			if ((mem[MEMB_PRXDUPD] & 0x24) == 0x20) {
 				mem[MEMB_PRXDUPD] ^= 4;
 				gdc.clock |= 3;
-				CopyMemory(gdc.s.para + GDC_SYNC, sync400m, 8);
+				CopyMemory(gdc.s.para + GDC_SYNC, gdcslavesync[3], 8);
 				gdc.s.para[GDC_PITCH] = 80;
 				gdcs.grphdisp |= GDCSCRN_EXT;
 				mem[MEMB_PRXDUPD] |= 0x08;
 			}
 		}
 		else {
-			crtmode &= 1;
 			if ((mem[MEMB_PRXDUPD] & 0x24) == 0x24) {
 				mem[MEMB_PRXDUPD] ^= 4;
 				gdc.clock &= ~3;
-				CopyMemory(gdc.s.para + GDC_SYNC,
-							(mem[MEMB_PRXCRT] & 0x40)?sync200m:sync200l, 8);
+#if defined(SUPPORT_CRT31KHZ)
+				if (rate & 4) slave = 4;
+				else
+#endif
+				slave = (mem[MEMB_PRXCRT] & 0x40)?2:0;
+				CopyMemory(gdc.s.para + GDC_SYNC, gdcslavesync[slave], 8);
 				gdc.s.para[GDC_PITCH] = 40;
 				gdcs.grphdisp |= GDCSCRN_EXT;
 				mem[MEMB_PRXDUPD] |= 0x08;
 			}
-			if (crtmode == 1) {				// UPPER
+			if (crtmode & 1) {				// UPPER
 				gdc.s.para[GDC_SCROLL+0] = (200*40) & 0xff;
 				gdc.s.para[GDC_SCROLL+1] = (200*40) >> 8;
 			}
@@ -487,6 +513,8 @@ void bios0x18_42(REG8 mode) {
 			gdc.s.para[GDC_CSRFORM] = 1;
 		}
 #if defined(SUPPORT_CRT31KHZ)
+		mem[MEMB_CRT_BIOS] &= ~3;
+		mem[MEMB_CRT_BIOS] |= crtmode;
 	}
 #endif
 	if (crtmode != 3) {
@@ -516,7 +544,6 @@ static void setbiosgdc(UINT32 csrw, cons
 	mem[MEMB_PRXDUPD] |= ope;
 }
 
-
 static void bios0x18_47(void) {
 
 	UCWTBL		ucw;
@@ -691,12 +718,37 @@ static void bios0x18_49(void) {
 }
 
 
+// ---- PC-9821
+
+#if defined(SUPPORT_PC9821)
+static void bios0x18_4d(REG8 mode) {
+
+	if ((mem[0x45c] & 0x40) &&
+		((mem[MEMB_CRT_BIOS] & 3) == 2)) {
+		if (mode == 0) {
+			gdc_analogext(FALSE);
+			mem[MEMB_PRXDUPD] &= ~0x7f;
+			mem[MEMB_PRXDUPD] |= 0x04;
+		}
+		else if (mode == 1) {
+			gdc_analogext(TRUE);
+			mem[MEMB_PRXDUPD] |= 0x80;
+		}
+		else {
+			mem[MEMB_PRXDUPD] |= 0x04;
+		}
+	}
+}
+#endif
+
+
 // ----
 
 void bios0x18(void) {
 
 	union {
 		BOOL	b;
+		REG8	r8;
 		UINT16	w;
 		UINT32	d;
 		UINT8	col[4];
@@ -803,7 +855,7 @@ void bios0x18(void) {
 //			screenupdate |= 2;
  			break;
 
-		case 0x0f:						// 複数の表示領域の設定(15/24khz)
+		case 0x0f:						// 複数の表示領域の設定
 			gdc_forceready(GDCWORK_MASTER);
 			bios0x18_0f(CPU_BX, CPU_CX, CPU_DH, CPU_DL);
 			break;
@@ -884,7 +936,18 @@ void bios0x18(void) {
 			if (mem[MEMB_CRT_BIOS] & 0x80) {
 				gdc_forceready(GDCWORK_MASTER);
 				gdc_forceready(GDCWORK_SLAVE);
-				CPU_AL = bios0x18_30(CPU_AL, CPU_BH);
+				tmp.r8 = bios0x18_30(CPU_AL, CPU_BH);
+				CPU_AH = tmp.r8;
+				if (tmp.r8 == 0x05) {
+					CPU_AL = 0;
+					CPU_BH = 0;
+					TRACEOUT(("success"));
+				}
+				else {
+					CPU_AL = 1;
+					CPU_BH = 1;
+					TRACEOUT(("failure"));
+				}
 			}
 			break;
 
@@ -948,6 +1011,11 @@ void bios0x18(void) {
 				}
 			}
 			break;
+#if defined(SUPPORT_PC9821)
+		case 0x4d:
+			bios0x18_4d(CPU_CH);
+			break;
+#endif
 	}
 }