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| version 1.16, 2004/01/29 09:41:49 | version 1.23, 2004/03/06 18:25:35 |
|---|---|
| Line 17 enum { | Line 17 enum { |
| }; | }; |
| static BYTE mtr_c = 0; | |
| static UINT mtr_r = 0; | |
| // ---- FDD | // ---- FDD |
| static void setfdcmode(REG8 drv, REG8 type, REG8 rpm) { | static BOOL setfdcmode(REG8 drv, REG8 type, REG8 rpm) { |
| if (drv < 4) { | if (drv >= 4) { |
| fdc.chgreg = type; | return(FAILURE); |
| fdc.rpm[drv] = rpm; | |
| if (type & 2) { | |
| CTRL_FDMEDIA = DISKTYPE_2HD; | |
| } | |
| else { | |
| CTRL_FDMEDIA = DISKTYPE_2DD; | |
| } | |
| } | } |
| if ((rpm) && (!fdc.support144)) { | |
| return(FAILURE); | |
| } | |
| fdc.chgreg = type; | |
| fdc.rpm[drv] = rpm; | |
| if (type & 2) { | |
| CTRL_FDMEDIA = DISKTYPE_2HD; | |
| } | |
| else { | |
| CTRL_FDMEDIA = DISKTYPE_2DD; | |
| } | |
| return(SUCCESS); | |
| } | } |
| void fddbios_equip(REG8 type, BOOL clear) { | void fddbios_equip(REG8 type, BOOL clear) { |
| Line 47 void fddbios_equip(REG8 type, BOOL clear | Line 48 void fddbios_equip(REG8 type, BOOL clear |
| } | } |
| if (type & 1) { | if (type & 1) { |
| diskequip &= 0xfff0; | diskequip &= 0xfff0; |
| diskequip |= 0x0003; | diskequip |= (fdc.equip & 0x0f); |
| } | } |
| else { | else { |
| diskequip &= 0xf0ff; | diskequip &= 0x0fff; |
| diskequip |= 0x0300; | diskequip |= (fdc.equip & 0x0f) << 12; |
| } | } |
| SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip); | SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip); |
| } | } |
| Line 92 static BOOL biosfd_seek(REG8 track, BOOL | Line 93 static BOOL biosfd_seek(REG8 track, BOOL |
| } | } |
| } | } |
| fdc.ncn = track; | fdc.ncn = track; |
| mtr_c = track; | |
| if (fdd_seek()) { | if (fdd_seek()) { |
| return(FAILURE); | return(FAILURE); |
| } | } |
| Line 160 static void fdd_int(int result) { | Line 160 static void fdd_int(int result) { |
| case 0x0a: // READ ID | case 0x0a: // READ ID |
| case 0x0d: // フォーマット | case 0x0d: // フォーマット |
| break; | break; |
| default: | default: |
| return; | return; |
| } | } |
| Line 196 static void fdd_int(int result) { | Line 197 static void fdd_int(int result) { |
| fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; | fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; |
| fdcsend_error7(); | fdcsend_error7(); |
| break; | break; |
| default: | |
| return; | |
| } | } |
| if (fdc.chgreg & 1) { | |
| mem[0x0055e] &= ~(0x01 << fdc.us); | |
| } | |
| else { | |
| mem[0x0055f] &= ~(0x10 << fdc.us); | |
| } | |
| CPU_IP = BIOSOFST_WAIT; | |
| } | } |
| #if 1 | #if 1 |
| Line 282 static REG8 fdd_operate(REG8 type, REG8 | Line 293 static REG8 fdd_operate(REG8 type, REG8 |
| BYTE hd; | BYTE hd; |
| int result = FDCBIOS_NORESULT; | int result = FDCBIOS_NORESULT; |
| UINT32 addr; | UINT32 addr; |
| UINT8 mtr_c; | |
| UINT mtr_r; | |
| mtr_c = 0xff; | mtr_c = fdc.ncn; |
| mtr_r = 0; | mtr_r = 0; |
| // とりあえずBIOSの時は無視する | // とりあえずBIOSの時は無視する |
| Line 291 static REG8 fdd_operate(REG8 type, REG8 | Line 304 static REG8 fdd_operate(REG8 type, REG8 |
| // TRACE_("int 1Bh", CPU_AH); | // TRACE_("int 1Bh", CPU_AH); |
| setfdcmode(CPU_AL & 3, type, rpm); | if (setfdcmode((REG8)(CPU_AL & 3), type, rpm) != SUCCESS) { |
| return(0x40); | |
| } | |
| if ((CPU_AH & 0x0f) != 0x0a) { | if ((CPU_AH & 0x0f) != 0x0a) { |
| fdc.crcn = 0; | fdc.crcn = 0; |
| Line 322 static REG8 fdd_operate(REG8 type, REG8 | Line 337 static REG8 fdd_operate(REG8 type, REG8 |
| return(0x68); // 新センスは 両用ドライブ情報も | return(0x68); // 新センスは 両用ドライブ情報も |
| } | } |
| if (CPU_AH == 0xc4) { // ver0.31 | if (CPU_AH == 0xc4) { // ver0.31 |
| if (np2cfg.usefd144) { | if (fdc.support144) { |
| return(0x6c); | return(0x6c); |
| } | } |
| return(0x68); | return(0x68); |
| Line 433 static REG8 fdd_operate(REG8 type, REG8 | Line 448 static REG8 fdd_operate(REG8 type, REG8 |
| } | } |
| if (CPU_AH & 0x80) { // ver0.30 | if (CPU_AH & 0x80) { // ver0.30 |
| ret_ah |= 8; // 1MB/640KB両用ドライブ | ret_ah |= 8; // 1MB/640KB両用ドライブ |
| if ((CPU_AH & 0x40) && | if ((CPU_AH & 0x40) && (fdc.support144)) { |
| (np2cfg.usefd144)) { // ver0.31 | |
| ret_ah |= 4; // 1.44対応ドライブ | ret_ah |= 4; // 1.44対応ドライブ |
| } | } |
| } | } |
| Line 477 static REG8 fdd_operate(REG8 type, REG8 | Line 491 static REG8 fdd_operate(REG8 type, REG8 |
| else { | else { |
| accesssize = size; | accesssize = size; |
| } | } |
| i286_memx_read(addr, fdc.buf, accesssize); | MEML_READ(addr, fdc.buf, accesssize); |
| if (fdd_write()) { | if (fdd_write()) { |
| break; | break; |
| } | } |
| Line 546 static REG8 fdd_operate(REG8 type, REG8 | Line 560 static REG8 fdd_operate(REG8 type, REG8 |
| if (fdd_read()) { | if (fdd_read()) { |
| break; | break; |
| } | } |
| i286_memx_write(addr, fdc.buf, accesssize); | MEML_WRITE(addr, fdc.buf, accesssize); |
| addr += accesssize; | addr += accesssize; |
| size -= accesssize; | size -= accesssize; |
| mtr_r += accesssize; // ver0.26 | mtr_r += accesssize; // ver0.26 |
| Line 647 static REG8 fdd_operate(REG8 type, REG8 | Line 661 static REG8 fdd_operate(REG8 type, REG8 |
| fdd_formatinit(); | fdd_formatinit(); |
| pos = CPU_BP; | pos = CPU_BP; |
| for (s=0; s<fdc.sc; s++) { | for (s=0; s<fdc.sc; s++) { |
| i286_memstr_read(CPU_ES, pos, ID, 4); | MEML_READSTR(CPU_ES, pos, ID, 4); |
| fdd_formating(ID); | fdd_formating(ID); |
| pos += 4; | pos += 4; |
| if (ID[3] < 8) { | if (ID[3] < 8) { |
| Line 661 static REG8 fdd_operate(REG8 type, REG8 | Line 675 static REG8 fdd_operate(REG8 type, REG8 |
| break; | break; |
| } | } |
| fdd_int(result); | fdd_int(result); |
| fddmtr_seek(fdc.us, mtr_c, mtr_r); | if (mtr_c != fdc.ncn) { |
| CPU_IP = BIOSOFST_WAIT; // ver0.30 | fddmtr_seek(fdc.us, mtr_c, mtr_r); |
| } | |
| return(ret_ah); | return(ret_ah); |
| } | } |
| Line 676 static UINT16 boot_fd1(REG8 type, REG8 r | Line 691 static UINT16 boot_fd1(REG8 type, REG8 r |
| UINT32 pos; | UINT32 pos; |
| UINT16 bootseg; | UINT16 bootseg; |
| setfdcmode(fdc.us, type, rpm); | if (setfdcmode(fdc.us, type, rpm) != SUCCESS) { |
| return(0); | |
| } | |
| if (biosfd_seek(0, 0)) { | if (biosfd_seek(0, 0)) { |
| return(0); | return(0); |
| } | } |
| Line 873 void bios0x1b(void) { | Line 890 void bios0x1b(void) { |
| i286_memword_write(CPU_SS, sp - 14, CPU_CX); // +4 | i286_memword_write(CPU_SS, sp - 14, CPU_CX); // +4 |
| i286_memword_write(CPU_SS, sp - 16, CPU_BX); // +2 | i286_memword_write(CPU_SS, sp - 16, CPU_BX); // +2 |
| i286_memword_write(CPU_SS, sp - 18, CPU_AX); // +0 | i286_memword_write(CPU_SS, sp - 18, CPU_AX); // +0 |
| #if 0 | |
| TRACEOUT(("bypass to %.4x:0018", seg << 8)); | TRACEOUT(("bypass to %.4x:0018", seg << 8)); |
| TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x", | TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x", |
| CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, | CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, |
| CPU_ES, CPU_BP)); | CPU_ES, CPU_BP)); |
| #endif | |
| sp -= 18; | sp -= 18; |
| CPU_SP = sp; | CPU_SP = sp; |
| CPU_BP = sp; | CPU_BP = sp; |
| Line 929 void bios0x1b(void) { | Line 948 void bios0x1b(void) { |
| ret_ah = 0x40; | ret_ah = 0x40; |
| break; | break; |
| } | } |
| #if 0 | #if 1 |
| TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \ | TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \ |
| "ES=%04x BP=%04x \nret=%02x", | "ES=%04x BP=%04x \nret=%02x", |
| i286_memword_read(CPU_SS, CPU_SP+2), | i286_memword_read(CPU_SS, CPU_SP+2), |