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| version 1.16, 2004/01/29 09:41:49 | version 1.17, 2004/01/29 10:04:05 |
|---|---|
| Line 160 static void fdd_int(int result) { | Line 160 static void fdd_int(int result) { |
| case 0x0a: // READ ID | case 0x0a: // READ ID |
| case 0x0d: // フォーマット | case 0x0d: // フォーマット |
| break; | break; |
| default: | default: |
| return; | return; |
| } | } |
| Line 196 static void fdd_int(int result) { | Line 197 static void fdd_int(int result) { |
| fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; | fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; |
| fdcsend_error7(); | fdcsend_error7(); |
| break; | break; |
| default: | |
| return; | |
| } | |
| if (fdc.chgreg & 1) { | |
| mem[0x0055e] &= ~(0x01 << fdc.us); | |
| } | |
| else { | |
| mem[0x0055f] &= ~(0x10 << fdc.us); | |
| } | } |
| CPU_IP = BIOSOFST_WAIT; | |
| } | } |
| #if 1 | #if 1 |
| Line 291 static REG8 fdd_operate(REG8 type, REG8 | Line 302 static REG8 fdd_operate(REG8 type, REG8 |
| // TRACE_("int 1Bh", CPU_AH); | // TRACE_("int 1Bh", CPU_AH); |
| setfdcmode(CPU_AL & 3, type, rpm); | setfdcmode((REG8)(CPU_AL & 3), type, rpm); |
| if ((CPU_AH & 0x0f) != 0x0a) { | if ((CPU_AH & 0x0f) != 0x0a) { |
| fdc.crcn = 0; | fdc.crcn = 0; |
| Line 662 static REG8 fdd_operate(REG8 type, REG8 | Line 673 static REG8 fdd_operate(REG8 type, REG8 |
| } | } |
| fdd_int(result); | fdd_int(result); |
| fddmtr_seek(fdc.us, mtr_c, mtr_r); | fddmtr_seek(fdc.us, mtr_c, mtr_r); |
| CPU_IP = BIOSOFST_WAIT; // ver0.30 | |
| return(ret_ah); | return(ret_ah); |
| } | } |