| version 1.3, 2003/10/21 11:22:05 | version 1.26, 2004/03/31 19:23:37 | 
| Line 1 | Line 1 | 
 | #include        "compiler.h" | #include        "compiler.h" | 
| #include        "i286.h" | #include        "cpucore.h" | 
| #include        "memory.h" |  | 
 | #include        "pccore.h" | #include        "pccore.h" | 
 | #include        "iocore.h" | #include        "iocore.h" | 
 |  | #include        "scsicmd.h" | 
 | #include        "bios.h" | #include        "bios.h" | 
 | #include        "biosmem.h" | #include        "biosmem.h" | 
 |  | #include        "sxsibios.h" | 
 | #include        "fddfile.h" | #include        "fddfile.h" | 
 | #include        "fdd_mtr.h" | #include        "fdd_mtr.h" | 
 | #include        "sxsi.h" | #include        "sxsi.h" | 
| Line 16  enum { | Line 17  enum { | 
 | }; | }; | 
 |  |  | 
 |  |  | 
| char    fdmode = 0; | // ---- FDD | 
| static  BYTE    work[65536]; |  | 
| static  BYTE    mtr_c = 0; |  | 
| static  UINT    mtr_r = 0; |  | 
 |  |  | 
 |  | static BOOL setfdcmode(REG8 drv, REG8 type, REG8 rpm) { | 
 |  |  | 
| // ---- FDD | if (drv >= 4) { | 
|  | return(FAILURE); | 
|  | } | 
|  | if ((rpm) && (!fdc.support144)) { | 
|  | return(FAILURE); | 
|  | } | 
|  | fdc.chgreg = type; | 
|  | fdc.rpm[drv] = rpm; | 
|  | if (type & 2) { | 
|  | CTRL_FDMEDIA = DISKTYPE_2HD; | 
|  | } | 
|  | else { | 
|  | CTRL_FDMEDIA = DISKTYPE_2DD; | 
|  | } | 
|  | return(SUCCESS); | 
|  | } | 
 |  |  | 
| static void init_fdd_equip(void) { | void fddbios_equip(REG8 type, BOOL clear) { | 
 |  |  | 
| UINT16  diskequip; | REG16   diskequip; | 
 |  |  | 
 | diskequip = GETBIOSMEM16(MEMW_DISK_EQUIP); | diskequip = GETBIOSMEM16(MEMW_DISK_EQUIP); | 
| diskequip &= 0x0f00; | if (clear) { | 
| diskequip |= (UINT16)(~fdmode) & 3; | diskequip &= 0x0f00; | 
| diskequip |= (UINT16)fdmode << 12; | } | 
|  | if (type & 1) { | 
|  | diskequip &= 0xfff0; | 
|  | diskequip |= (fdc.equip & 0x0f); | 
|  | } | 
|  | else { | 
|  | diskequip &= 0x0fff; | 
|  | diskequip |= (fdc.equip & 0x0f) << 12; | 
|  | } | 
 | SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip); | SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip); | 
 | } | } | 
 |  |  | 
 | static void biosfd_setchrn(void) { | static void biosfd_setchrn(void) { | 
 |  |  | 
| fdc.C = I286_CL; | fdc.C = CPU_CL; | 
| fdc.H = I286_DH; | fdc.H = CPU_DH; | 
| fdc.R = I286_DL; | fdc.R = CPU_DL; | 
| fdc.N = I286_CH; | fdc.N = CPU_CH; | 
 | } | } | 
 |  |  | 
 | #if 0 | #if 0 | 
| Line 60  static void biosfd_resultout(UINT32 resu | Line 82  static void biosfd_resultout(UINT32 resu | 
 | } | } | 
 | #endif | #endif | 
 |  |  | 
| static BOOL biosfd_seek(BYTE track, BOOL ndensity) { | static BOOL biosfd_seek(REG8 track, BOOL ndensity) { | 
 |  |  | 
 | if (ndensity) { | if (ndensity) { | 
 | if (track < 42) { | if (track < 42) { | 
| Line 71  static BOOL biosfd_seek(BYTE track, BOOL | Line 93  static BOOL biosfd_seek(BYTE track, BOOL | 
 | } | } | 
 | } | } | 
 | fdc.ncn = track; | fdc.ncn = track; | 
 | mtr_c = track; |  | 
 | if (fdd_seek()) { | if (fdd_seek()) { | 
 | return(FAILURE); | return(FAILURE); | 
 | } | } | 
 | return(SUCCESS); | return(SUCCESS); | 
 | } | } | 
 |  |  | 
| static UINT16 fdfmt_biospara(BYTE fmt, BYTE rpm) {                                      // ver0.31 | static UINT16 fdfmt_biospara(REG8 type, REG8 rpm, REG8 fmt) { | 
 |  |  | 
| UINT16  seg; | UINT    seg; | 
| UINT16  off; | UINT    off; | 
 | UINT16  n; | UINT16  n; | 
 |  |  | 
 | n = fdc.N; | n = fdc.N; | 
 | if (n >= 4) { | if (n >= 4) { | 
 | n = 3; | n = 3; | 
 | } | } | 
| if (CTRL_FDMEDIA == DISKTYPE_2HD) { | if (type & 2) { | 
 | seg = GETBIOSMEM16(MEMW_F2HD_P_SEG); | seg = GETBIOSMEM16(MEMW_F2HD_P_SEG); | 
 | off = GETBIOSMEM16(MEMW_F2HD_P_OFF); | off = GETBIOSMEM16(MEMW_F2HD_P_OFF); | 
 | } | } | 
| Line 100  static UINT16 fdfmt_biospara(BYTE fmt, B | Line 121  static UINT16 fdfmt_biospara(BYTE fmt, B | 
 | off = 0x2361;                                                                   // see bios.cpp | off = 0x2361;                                                                   // see bios.cpp | 
 | } | } | 
 | off += fdc.us * 2; | off += fdc.us * 2; | 
| off = i286_memword_read(seg, off); | off = MEML_READ16(seg, off); | 
 | off += n * 8; | off += n * 8; | 
| if (!(I286_AH & 0x40)) { | if (!(CPU_AH & 0x40)) { | 
 | off += 4; | off += 4; | 
 | } | } | 
 | if (fmt) { | if (fmt) { | 
 | off += 2; | off += 2; | 
 | } | } | 
| return(i286_memword_read(seg, off)); | return(MEML_READ16(seg, off)); | 
 | } | } | 
 |  |  | 
 | static void change_rpm(BYTE rpm) {                                                                      // ver0.31 |  | 
 |  |  | 
 | if (np2cfg.usefd144) { |  | 
 | fdc.rpm = rpm; |  | 
 | } |  | 
 | } |  | 
 |  |  | 
 |  |  | 
 |  |  | 
 | enum { | enum { | 
 | FDCBIOS_NORESULT, | FDCBIOS_NORESULT, | 
| Line 137  static void fdd_int(int result) { | Line 150  static void fdd_int(int result) { | 
 | if (result == FDCBIOS_NORESULT) {                                               // ver0.29 | if (result == FDCBIOS_NORESULT) {                                               // ver0.29 | 
 | return; | return; | 
 | } | } | 
| switch(I286_AH & 0x0f) { | switch(CPU_AH & 0x0f) { | 
 | case 0x00:                                                              // シーク | case 0x00:                                                              // シーク | 
 | case 0x01:                                                              // ベリファイ | case 0x01:                                                              // ベリファイ | 
 | case 0x02:                                                              // 診断の為の読み込み | case 0x02:                                                              // 診断の為の読み込み | 
| Line 147  static void fdd_int(int result) { | Line 160  static void fdd_int(int result) { | 
 | case 0x0a:                                                              // READ ID | case 0x0a:                                                              // READ ID | 
 | case 0x0d:                                                              // フォーマット | case 0x0d:                                                              // フォーマット | 
 | break; | break; | 
 |  |  | 
 | default: | default: | 
 | return; | return; | 
 | } | } | 
| Line 183  static void fdd_int(int result) { | Line 197  static void fdd_int(int result) { | 
 | fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; | fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; | 
 | fdcsend_error7(); | fdcsend_error7(); | 
 | break; | break; | 
 |  |  | 
 |  | default: | 
 |  | return; | 
 | } | } | 
 |  | if (fdc.chgreg & 1) { | 
 |  | mem[0x0055e] &= ~(0x01 << fdc.us); | 
 |  | } | 
 |  | else { | 
 |  | mem[0x0055f] &= ~(0x10 << fdc.us); | 
 |  | } | 
 |  | CPU_IP = BIOSOFST_WAIT; | 
 | } | } | 
 |  |  | 
 | #if 1 | #if 1 | 
| Line 197  static struct { | Line 221  static struct { | 
 |  |  | 
 | static void b0patch(void) { | static void b0patch(void) { | 
 |  |  | 
| if ((!b0p.flg) || (b0p.cx != I286_CX) || (b0p.dx != I286_DX)) { | if ((!b0p.flg) || (b0p.cx != CPU_CX) || (b0p.dx != CPU_DX)) { | 
 | b0p.flg = TRUE; | b0p.flg = TRUE; | 
 | b0p.pos = 0; | b0p.pos = 0; | 
| b0p.cx = I286_CX; | b0p.cx = CPU_CX; | 
| b0p.dx = I286_DX; | b0p.dx = CPU_DX; | 
 | } | } | 
 | else { | else { | 
 | if (!b0p.pos) { | if (!b0p.pos) { | 
 | UINT32  addr; | UINT32  addr; | 
 | UINT    size; | UINT    size; | 
 | UINT    cnt; | UINT    cnt; | 
| BYTE    c; | REG8    c; | 
| BYTE    cl; | REG8    cl; | 
| BYTE    last; | REG8    last; | 
| addr = ES_BASE + I286_BP; | addr = ES_BASE + CPU_BP; | 
| size = I286_BX; | size = CPU_BX; | 
 | cnt = 0; | cnt = 0; | 
 | last = 0; | last = 0; | 
 | while(size--) { | while(size--) { | 
 | c = i286_memoryread(addr++); | c = i286_memoryread(addr++); | 
 | cl = 0; | cl = 0; | 
 | do { | do { | 
| BYTE now = c & 0x80; | REG8 now = c & 0x80; | 
 | c <<= 1; | c <<= 1; | 
 | b0p.pos++; | b0p.pos++; | 
 | if (now == last) { | if (now == last) { | 
| Line 239  static void b0patch(void) { | Line 263  static void b0patch(void) { | 
 | } | } | 
 | } | } | 
 | } | } | 
| if ((b0p.pos >> 3) < I286_BX) { | if ((b0p.pos >> 3) < CPU_BX) { | 
 | UINT32 addr; | UINT32 addr; | 
| BYTE c; | REG8 c; | 
| addr = ES_BASE + I286_BP + (b0p.pos >> 3); | addr = ES_BASE + CPU_BP + (b0p.pos >> 3); | 
 | c = i286_memoryread(addr); | c = i286_memoryread(addr); | 
 | c ^= (1 << (b0p.pos & 7)); | c ^= (1 << (b0p.pos & 7)); | 
 | b0p.pos++; | b0p.pos++; | 
| Line 256  static void b0clr(void) { | Line 280  static void b0clr(void) { | 
 | } | } | 
 | #endif | #endif | 
 |  |  | 
| static BYTE fdd_operate(BYTE type, BOOL ndensity, BYTE rpm) {           // ver0.31 | static REG8 fdd_operate(REG8 type, REG8 rpm, BOOL ndensity) { | 
 |  |  | 
| BYTE    ret_ah = 0x60; | REG8    ret_ah = 0x60; | 
 | UINT16  size; | UINT16  size; | 
 | UINT16  pos; | UINT16  pos; | 
 | UINT16  accesssize; | UINT16  accesssize; | 
| Line 269  static BYTE fdd_operate(BYTE type, BOOL | Line 293  static BYTE fdd_operate(BYTE type, BOOL | 
 | BYTE    hd; | BYTE    hd; | 
 | int             result = FDCBIOS_NORESULT; | int             result = FDCBIOS_NORESULT; | 
 | UINT32  addr; | UINT32  addr; | 
 |  | UINT8   mtr_c; | 
 |  | UINT    mtr_r; | 
 |  |  | 
| mtr_c = 0xff; | mtr_c = fdc.ncn; | 
 | mtr_r = 0; | mtr_r = 0; | 
 |  |  | 
 |  |  | 
 | // とりあえずBIOSの時は無視する | // とりあえずBIOSの時は無視する | 
 | fdc.mf = 0xff;                                          // ver0.29 | fdc.mf = 0xff;                                          // ver0.29 | 
 |  |  | 
| //      TRACE_("int 1Bh", I286_AH); | //      TRACE_("int 1Bh", CPU_AH); | 
 |  |  | 
| change_rpm(rpm);                                                                                                // ver0.31 | if (setfdcmode((REG8)(CPU_AL & 3), type, rpm) != SUCCESS) { | 
| if ((I286_AH & 0x0f) != 0x0a) { | return(0x40); | 
|  | } | 
|  |  | 
|  | if ((CPU_AH & 0x0f) != 0x0a) { | 
 | fdc.crcn = 0; | fdc.crcn = 0; | 
 | } | } | 
| if ((I286_AH & 0x0f) != 0x03) { | if ((CPU_AH & 0x0f) != 0x03) { | 
| CTRL_FDMEDIA = type; | if (type & 2) { | 
| switch(type) { | if (pic.pi[1].imr & PIC_INT42) { | 
| case DISKTYPE_2HD: | return(0x40); | 
| if (pic.pi[1].imr & PIC_INT42) { | } | 
| return(0xd0); |  | 
| } |  | 
| break; |  | 
| case DISKTYPE_2DD: |  | 
| if (pic.pi[1].imr & PIC_INT41) { |  | 
| return(0xd0); |  | 
| } |  | 
| break; |  | 
 | } | } | 
| if (fdc.us != (I286_AL & 0x03)) { | else { | 
| fdc.us = I286_AL & 0x03; | if (pic.pi[1].imr & PIC_INT41) { | 
|  | return(0x40); | 
|  | } | 
|  | } | 
|  | if (fdc.us != (CPU_AL & 0x03)) { | 
|  | fdc.us = CPU_AL & 0x03; | 
 | fdc.crcn = 0; | fdc.crcn = 0; | 
 | } | } | 
| hd = ((I286_DH) ^ (I286_AL >> 2)) & 1; | hd = ((CPU_DH) ^ (CPU_AL >> 2)) & 1; | 
 | if (fdc.hd != hd) { | if (fdc.hd != hd) { | 
 | fdc.hd = hd; | fdc.hd = hd; | 
 | fdc.crcn = 0; | fdc.crcn = 0; | 
 | } | } | 
 | if (!fdd_diskready(fdc.us)) { | if (!fdd_diskready(fdc.us)) { | 
 | fdd_int(FDCBIOS_NONREADY); | fdd_int(FDCBIOS_NONREADY); | 
| if (I286_AH == 0x84) {                                                          // ver0.28 | if (CPU_AH == 0x84) {                                                           // ver0.28 | 
 | return(0x68);                   // 新センスは 両用ドライブ情報も | return(0x68);                   // 新センスは 両用ドライブ情報も | 
 | } | } | 
| if (I286_AH == 0xc4) {                                                          // ver0.31 | if (CPU_AH == 0xc4) {                                                           // ver0.31 | 
| if (np2cfg.usefd144) { | if (fdc.support144) { | 
 | return(0x6c); | return(0x6c); | 
 | } | } | 
 | return(0x68); | return(0x68); | 
| Line 328  static BYTE fdd_operate(BYTE type, BOOL | Line 353  static BYTE fdd_operate(BYTE type, BOOL | 
 | } | } | 
 | } | } | 
 |  |  | 
| switch(I286_AH & 0x0f) { | switch(CPU_AH & 0x0f) { | 
 | case 0x00:                                                              // シーク | case 0x00:                                                              // シーク | 
| if (I286_AH & 0x10) { | if (CPU_AH & 0x10) { | 
| if (!biosfd_seek(I286_CL, ndensity)) { | if (!biosfd_seek(CPU_CL, ndensity)) { | 
 | result = FDCBIOS_SEEKSUCCESS; | result = FDCBIOS_SEEKSUCCESS; | 
 | } | } | 
 | else { | else { | 
| Line 342  static BYTE fdd_operate(BYTE type, BOOL | Line 367  static BYTE fdd_operate(BYTE type, BOOL | 
 | break; | break; | 
 |  |  | 
 | case 0x01:                                                              // ベリファイ | case 0x01:                                                              // ベリファイ | 
| if (I286_AH & 0x10) { | if (CPU_AH & 0x10) { | 
| if (!biosfd_seek(I286_CL, ndensity)) { | if (!biosfd_seek(CPU_CL, ndensity)) { | 
 | result = FDCBIOS_SEEKSUCCESS; | result = FDCBIOS_SEEKSUCCESS; | 
 | } | } | 
 | else { | else { | 
| Line 353  static BYTE fdd_operate(BYTE type, BOOL | Line 378  static BYTE fdd_operate(BYTE type, BOOL | 
 | } | } | 
 | } | } | 
 | biosfd_setchrn(); | biosfd_setchrn(); | 
| para = fdfmt_biospara(0, rpm); | para = fdfmt_biospara(type, rpm, 0); | 
 | if (!para) { | if (!para) { | 
 | ret_ah = 0xd0; | ret_ah = 0xd0; | 
 | break; | break; | 
| Line 364  static BYTE fdd_operate(BYTE type, BOOL | Line 389  static BYTE fdd_operate(BYTE type, BOOL | 
 | else { | else { | 
 | secsize = 128 << 8; | secsize = 128 << 8; | 
 | } | } | 
| size = I286_BX; | size = CPU_BX; | 
 | while(size) { | while(size) { | 
 | if (size > secsize) { | if (size > secsize) { | 
 | accesssize = secsize; | accesssize = secsize; | 
| Line 377  static BYTE fdd_operate(BYTE type, BOOL | Line 402  static BYTE fdd_operate(BYTE type, BOOL | 
 | } | } | 
 | size -= accesssize; | size -= accesssize; | 
 | mtr_r += accesssize;                                            // ver0.26 | mtr_r += accesssize;                                            // ver0.26 | 
| if ((fdc.R++ == (BYTE)para) && (I286_AH & 0x80) && (!fdc.hd)) { | if ((fdc.R++ == (UINT8)para) && | 
|  | (CPU_AH & 0x80) && (!fdc.hd)) { | 
 | fdc.hd = 1; | fdc.hd = 1; | 
 | fdc.H = 1; | fdc.H = 1; | 
 | fdc.R = 1; | fdc.R = 1; | 
| Line 397  static BYTE fdd_operate(BYTE type, BOOL | Line 423  static BYTE fdd_operate(BYTE type, BOOL | 
 | break; | break; | 
 |  |  | 
 | case 0x03:                                                              // 初期化 | case 0x03:                                                              // 初期化 | 
| init_fdd_equip(); | fddbios_equip(type, FALSE); | 
 | ret_ah = 0x00; | ret_ah = 0x00; | 
 | break; | break; | 
 |  |  | 
| Line 409  static BYTE fdd_operate(BYTE type, BOOL | Line 435  static BYTE fdd_operate(BYTE type, BOOL | 
 | else if (fdd_diskprotect(fdc.us)) { | else if (fdd_diskprotect(fdc.us)) { | 
 | ret_ah = 0x10; | ret_ah = 0x10; | 
 | } | } | 
| if (I286_AL & 0x80) {                           // 2HD | if (CPU_AL & 0x80) {                            // 2HD | 
 | ret_ah |= 0x01; | ret_ah |= 0x01; | 
 | } | } | 
 | else {                                                          // 2DD | else {                                                          // 2DD | 
| Line 420  static BYTE fdd_operate(BYTE type, BOOL | Line 446  static BYTE fdd_operate(BYTE type, BOOL | 
 | ret_ah |= 0x04; | ret_ah |= 0x04; | 
 | } | } | 
 | } | } | 
| if (I286_AH & 0x80) {                           // ver0.30 | if (CPU_AH & 0x80) {                            // ver0.30 | 
 | ret_ah |= 8;                                    // 1MB/640KB両用ドライブ | ret_ah |= 8;                                    // 1MB/640KB両用ドライブ | 
| if ((I286_AH & 0x40) && | if ((CPU_AH & 0x40) && (fdc.support144)) { | 
| (np2cfg.usefd144)) {            // ver0.31 |  | 
 | ret_ah |= 4;                            // 1.44対応ドライブ | ret_ah |= 4;                            // 1.44対応ドライブ | 
 | } | } | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | case 0x05:                                                              // データの書き込み | case 0x05:                                                              // データの書き込み | 
| if (I286_AH & 0x10) { | if (CPU_AH & 0x10) { | 
| if (!biosfd_seek(I286_CL, ndensity)) { | if (!biosfd_seek(CPU_CL, ndensity)) { | 
 | result = FDCBIOS_SEEKSUCCESS; | result = FDCBIOS_SEEKSUCCESS; | 
 | } | } | 
 | else { | else { | 
| Line 441  static BYTE fdd_operate(BYTE type, BOOL | Line 466  static BYTE fdd_operate(BYTE type, BOOL | 
 | } | } | 
 | } | } | 
 | biosfd_setchrn(); | biosfd_setchrn(); | 
| para = fdfmt_biospara(0, rpm); | para = fdfmt_biospara(type, rpm, 0); | 
 | if (!para) { | if (!para) { | 
 | ret_ah = 0xd0; | ret_ah = 0xd0; | 
 | break; | break; | 
| Line 457  static BYTE fdd_operate(BYTE type, BOOL | Line 482  static BYTE fdd_operate(BYTE type, BOOL | 
 | else { | else { | 
 | secsize = 128 << 8; | secsize = 128 << 8; | 
 | } | } | 
| size = I286_BX; | size = CPU_BX; | 
| addr = ES_BASE + I286_BP; | addr = ES_BASE + CPU_BP; | 
 | while(size) { | while(size) { | 
 | if (size > secsize) { | if (size > secsize) { | 
 | accesssize = secsize; | accesssize = secsize; | 
| Line 466  static BYTE fdd_operate(BYTE type, BOOL | Line 491  static BYTE fdd_operate(BYTE type, BOOL | 
 | else { | else { | 
 | accesssize = size; | accesssize = size; | 
 | } | } | 
| i286_memx_read(addr, fdc.buf, accesssize); | MEML_READ(addr, fdc.buf, accesssize); | 
 | if (fdd_write()) { | if (fdd_write()) { | 
 | break; | break; | 
 | } | } | 
 | addr += accesssize; | addr += accesssize; | 
 | size -= accesssize; | size -= accesssize; | 
 | mtr_r += accesssize;                                            // ver0.26 | mtr_r += accesssize;                                            // ver0.26 | 
| if ((fdc.R++ == (BYTE)para) && (I286_AH & 0x80) && (!fdc.hd)) { | if ((fdc.R++ == (UINT8)para) && | 
|  | (CPU_AH & 0x80) && (!fdc.hd)) { | 
 | fdc.hd = 1; | fdc.hd = 1; | 
 | fdc.H = 1; | fdc.H = 1; | 
 | fdc.R = 1; | fdc.R = 1; | 
| Line 494  static BYTE fdd_operate(BYTE type, BOOL | Line 520  static BYTE fdd_operate(BYTE type, BOOL | 
 |  |  | 
 | case 0x02:                                                              // 診断の為の読み込み | case 0x02:                                                              // 診断の為の読み込み | 
 | case 0x06:                                                              // データの読み込み | case 0x06:                                                              // データの読み込み | 
| if (I286_AH & 0x10) { | if (CPU_AH & 0x10) { | 
| if (!biosfd_seek(I286_CL, ndensity)) { | if (!biosfd_seek(CPU_CL, ndensity)) { | 
 | result = FDCBIOS_SEEKSUCCESS; | result = FDCBIOS_SEEKSUCCESS; | 
 | } | } | 
 | else { | else { | 
| Line 505  static BYTE fdd_operate(BYTE type, BOOL | Line 531  static BYTE fdd_operate(BYTE type, BOOL | 
 | } | } | 
 | } | } | 
 | biosfd_setchrn(); | biosfd_setchrn(); | 
| para = fdfmt_biospara(0, rpm); | para = fdfmt_biospara(type, rpm, 0); | 
 | if (!para) { | if (!para) { | 
 | ret_ah = 0xd0; | ret_ah = 0xd0; | 
 | break; | break; | 
| Line 522  static BYTE fdd_operate(BYTE type, BOOL | Line 548  static BYTE fdd_operate(BYTE type, BOOL | 
 | else { | else { | 
 | secsize = 128 << 8; | secsize = 128 << 8; | 
 | } | } | 
| size = I286_BX; | size = CPU_BX; | 
| addr = ES_BASE + I286_BP; | addr = ES_BASE + CPU_BP; | 
 | while(size) { | while(size) { | 
 | if (size > secsize) { | if (size > secsize) { | 
 | accesssize = secsize; | accesssize = secsize; | 
| Line 534  static BYTE fdd_operate(BYTE type, BOOL | Line 560  static BYTE fdd_operate(BYTE type, BOOL | 
 | if (fdd_read()) { | if (fdd_read()) { | 
 | break; | break; | 
 | } | } | 
| i286_memx_write(addr, fdc.buf, accesssize); | MEML_WRITE(addr, fdc.buf, accesssize); | 
 | addr += accesssize; | addr += accesssize; | 
 | size -= accesssize; | size -= accesssize; | 
 | mtr_r += accesssize;                                            // ver0.26 | mtr_r += accesssize;                                            // ver0.26 | 
| if (fdc.R++ == (BYTE)para) { | if (fdc.R++ == (UINT8)para) { | 
| if ((I286_AH & 0x80) && (!fdc.hd)) { | if ((CPU_AH & 0x80) && (!fdc.hd)) { | 
 | fdc.hd = 1; | fdc.hd = 1; | 
 | fdc.H = 1; | fdc.H = 1; | 
 | fdc.R = 1; | fdc.R = 1; | 
| Line 569  static BYTE fdd_operate(BYTE type, BOOL | Line 595  static BYTE fdd_operate(BYTE type, BOOL | 
 | #endif | #endif | 
 | } | } | 
 | #if 1 | #if 1 | 
| else if ((I286_AH & 0x0f) == 0x02) {    // ARS対策… | else if ((CPU_AH & 0x0f) == 0x02) {             // ARS対策… | 
 | ret_ah = 0x00; | ret_ah = 0x00; | 
 | result = FDCBIOS_READERROR; | result = FDCBIOS_READERROR; | 
 | } | } | 
| Line 587  static BYTE fdd_operate(BYTE type, BOOL | Line 613  static BYTE fdd_operate(BYTE type, BOOL | 
 | break; | break; | 
 |  |  | 
 | case 0x0a:                                              // READ ID | case 0x0a:                                              // READ ID | 
| fdc.mf = I286_AH & 0x40;                                                // ver0.29 | fdc.mf = CPU_AH & 0x40;                                                 // ver0.29 | 
| if (I286_AH & 0x10) {                                                   // ver0.28 | if (CPU_AH & 0x10) {                                                    // ver0.28 | 
| if (!biosfd_seek(I286_CL, ndensity)) { | if (!biosfd_seek(CPU_CL, ndensity)) { | 
 | result = FDCBIOS_SEEKSUCCESS; | result = FDCBIOS_SEEKSUCCESS; | 
 | } | } | 
 | else { | else { | 
| Line 609  static BYTE fdd_operate(BYTE type, BOOL | Line 635  static BYTE fdd_operate(BYTE type, BOOL | 
 | mtr_r += 128 << 8; | mtr_r += 128 << 8; | 
 | } | } | 
 | ret_ah = 0x00; | ret_ah = 0x00; | 
| I286_CL = fdc.C; | CPU_CL = fdc.C; | 
| I286_DH = fdc.H; | CPU_DH = fdc.H; | 
| I286_DL = fdc.R; | CPU_DL = fdc.R; | 
| I286_CH = fdc.N; | CPU_CH = fdc.N; | 
 | result = FDCBIOS_SUCCESS; | result = FDCBIOS_SUCCESS; | 
 | break; | break; | 
 |  |  | 
 | case 0x0d:                                              // フォーマット | case 0x0d:                                              // フォーマット | 
| if (I286_AH & 0x10) { | if (CPU_AH & 0x10) { | 
| biosfd_seek(I286_CL, ndensity); | biosfd_seek(CPU_CL, ndensity); | 
 | } | } | 
 | if (fdd_diskprotect(fdc.us)) { | if (fdd_diskprotect(fdc.us)) { | 
 | ret_ah = 0x70; | ret_ah = 0x70; | 
 | break; | break; | 
 | } | } | 
| fdc.d = I286_DL; | fdc.d = CPU_DL; | 
| fdc.N = I286_CH; | fdc.N = CPU_CH; | 
| para = fdfmt_biospara(1, rpm); | para = fdfmt_biospara(type, rpm, 1); | 
 | if (!para) { | if (!para) { | 
 | ret_ah = 0xd0; | ret_ah = 0xd0; | 
 | break; | break; | 
 | } | } | 
| fdc.sc = (BYTE)para; | fdc.sc = (UINT8)para; | 
 | fdd_formatinit(); | fdd_formatinit(); | 
| pos = I286_BP; | pos = CPU_BP; | 
 | for (s=0; s<fdc.sc; s++) { | for (s=0; s<fdc.sc; s++) { | 
| i286_memstr_read(I286_ES, pos, ID, 4); | MEML_READSTR(CPU_ES, pos, ID, 4); | 
 | fdd_formating(ID); | fdd_formating(ID); | 
 | pos += 4; | pos += 4; | 
 |  | if (ID[3] < 8) { | 
 |  | mtr_r += 128 << ID[3]; | 
 |  | } | 
 |  | else { | 
 |  | mtr_r += 128 << 8; | 
 |  | } | 
 | } | } | 
 | ret_ah = 0x00; | ret_ah = 0x00; | 
 | break; | break; | 
 | } | } | 
 | fdd_int(result); | fdd_int(result); | 
| fddmtr_seek(fdc.us, mtr_c, mtr_r); | if (mtr_c != fdc.ncn) { | 
| I286_IP = BIOSOFST_WAIT;                                                                                // ver0.30 | fddmtr_seek(fdc.us, mtr_c, mtr_r); | 
| return(ret_ah); |  | 
| } |  | 
|  |  | 
|  |  | 
| // ---- SASI |  | 
|  |  | 
| static void init_sasi_equip(void) { |  | 
|  |  | 
| UINT16  diskequip; |  | 
| UINT    i; |  | 
| UINT16  bit; |  | 
|  |  | 
| diskequip = GETBIOSMEM16(MEMW_DISK_EQUIP); |  | 
| diskequip &= 0xf0ff; |  | 
| for (i=0, bit=0x0100; i<2; i++, bit<<=1) { |  | 
| if (sxsi_hd[i].fname[0]) { |  | 
| diskequip |= bit; |  | 
| } |  | 
| } |  | 
| SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip); |  | 
| } |  | 
|  |  | 
| static void init_scsi_equip(void) { |  | 
|  |  | 
| UINT    i; |  | 
| BYTE    bit; |  | 
| UINT16  w; |  | 
|  |  | 
| mem[MEMB_DISK_EQUIPS] = 0; |  | 
| ZeroMemory(&mem[0x00460], 0x20); |  | 
| for (i=0, bit=1; i<2; i++, bit<<=1) { |  | 
| if (sxsi_hd[i+2].fname[0]) { |  | 
| mem[MEMB_DISK_EQUIPS] |= bit; |  | 
| mem[0x00460+i*4] = sxsi_hd[i+2].sectors; |  | 
| mem[0x00461+i*4] = sxsi_hd[i+2].surfaces; |  | 
| switch(sxsi_hd[i+2].size) { |  | 
| case 256: |  | 
| w = 0 << 12; |  | 
| break; |  | 
|  |  | 
| case 512: |  | 
| w = 1 << 12; |  | 
| break; |  | 
|  |  | 
| default: |  | 
| w = 2 << 12; |  | 
| break; |  | 
| } |  | 
| w |= sxsi_hd[i+2].tracks; |  | 
| SETBIOSMEM16(0x00462+i*4, w); |  | 
| } |  | 
| } |  | 
| } |  | 
|  |  | 
| static BYTE sxsi_pos(long *pos) { |  | 
|  |  | 
| SXSIHDD sxsi; |  | 
| int             np2drv; |  | 
|  |  | 
| *pos = 0; |  | 
| np2drv = (I286_AL & 0x20) >> 4; |  | 
| if ((I286_AL & 0x0f) >= 2) { |  | 
| return(0x60); |  | 
| } |  | 
| np2drv |= (I286_AL & 1); |  | 
| sxsi = &sxsi_hd[np2drv]; |  | 
| if (I286_AL & 0x80) { |  | 
| if ((I286_DL >= sxsi->sectors) || |  | 
| (I286_DH >= sxsi->surfaces) || |  | 
| (I286_CX >= sxsi->tracks)) { |  | 
| return(0xd0); |  | 
| } |  | 
| (*pos) = ((I286_CX * sxsi->surfaces) + I286_DH) * sxsi->sectors |  | 
| + I286_DL; |  | 
| } |  | 
| else { |  | 
| *pos = (I286_DL << 16) | I286_CX; |  | 
| if (!(I286_AL & 0x20)) { |  | 
| (*pos) &= 0x1fffff; |  | 
| } |  | 
| if ((*pos) >= sxsi->totals) { |  | 
| return(0xd0); |  | 
| } |  | 
| } |  | 
| return(0x00); |  | 
| } |  | 
|  |  | 
|  |  | 
| static BYTE sxsi_operate(BYTE type) { |  | 
|  |  | 
| BYTE    ret_ah = 0x00; |  | 
| BYTE    drv; |  | 
| long    pos; |  | 
| //      int             i; |  | 
|  |  | 
| drv = (I286_AL & 0x20) >> 4; |  | 
| if ((I286_AL & 0x0f) >= 2) { |  | 
| return(0x60); |  | 
| } |  | 
| drv |= (I286_AL & 1); |  | 
|  |  | 
| switch(I286_AH & 0x0f) { |  | 
| case 0x01:                                              // ベリファイ |  | 
| case 0x07:                                              // リトラクト |  | 
| case 0x0f:                                              // リトラクト |  | 
| break; |  | 
|  |  | 
| case 0x03:                                              // イニシャライズ |  | 
| if (type == HDDTYPE_SASI) { |  | 
| init_sasi_equip(); |  | 
| } |  | 
| else if (type == HDDTYPE_SCSI) { |  | 
| init_scsi_equip(); |  | 
| } |  | 
| break; |  | 
|  |  | 
| case 0x04:                                              // センス |  | 
| ret_ah = 0x00; |  | 
| if ((I286_AH == 0x04) && (type == HDDTYPE_SASI)) { |  | 
| ret_ah = 0x04; |  | 
| } |  | 
| else if ((I286_AH == 0x44) && (type == HDDTYPE_SCSI)) { |  | 
| I286_BX = 1; |  | 
| } |  | 
| else if (I286_AH == 0x84) { |  | 
| I286_BX = sxsi_hd[drv].size; |  | 
| I286_CX = sxsi_hd[drv].tracks; |  | 
| I286_DH = sxsi_hd[drv].surfaces; |  | 
| I286_DL = sxsi_hd[drv].sectors; |  | 
| } |  | 
| break; |  | 
|  |  | 
| case 0x05:                                              // データの書き込み |  | 
| i286_memx_read(ES_BASE + I286_BP, work, I286_BX); |  | 
| ret_ah = sxsi_pos(&pos); |  | 
| if (!ret_ah) { |  | 
| ret_ah = sxsi_write(I286_AL, pos, work, I286_BX); |  | 
| } |  | 
| break; |  | 
|  |  | 
| case 0x06:                                              // データの読み込み |  | 
| ret_ah = sxsi_pos(&pos); |  | 
| if (!ret_ah) { |  | 
| ret_ah = sxsi_read(I286_AL, pos, work, I286_BX); |  | 
| if (ret_ah < 0x20) { |  | 
| i286_memx_write(ES_BASE + I286_BP, work, I286_BX); |  | 
| } |  | 
| } |  | 
| break; |  | 
|  |  | 
| case 0x0d:                                              // フォーマット |  | 
| if (I286_DL) { |  | 
| ret_ah = 0x30; |  | 
| break; |  | 
| } |  | 
| i286_memstr_read(I286_ES, I286_BP, work, I286_BX); |  | 
| ret_ah = sxsi_pos(&pos); |  | 
| if (!ret_ah) { |  | 
| ret_ah = sxsi_format(I286_AL, pos); |  | 
| } |  | 
| break; |  | 
|  |  | 
| default: |  | 
| ret_ah = 0x40; |  | 
| break; |  | 
 | } | } | 
 | return(ret_ah); | return(ret_ah); | 
 | } | } | 
| Line 817  static BYTE sxsi_operate(BYTE type) { | Line 684  static BYTE sxsi_operate(BYTE type) { | 
 |  |  | 
 | // -------------------------------------------------------------------- BIOS | // -------------------------------------------------------------------- BIOS | 
 |  |  | 
| static UINT16 boot_fd1(BYTE rpm) {                                                                      // ver0.31 | static UINT16 boot_fd1(REG8 type, REG8 rpm) { | 
 |  |  | 
 | UINT    remain; | UINT    remain; | 
 | UINT    size; | UINT    size; | 
 | UINT32  pos; | UINT32  pos; | 
 | UINT16  bootseg; | UINT16  bootseg; | 
 |  |  | 
| change_rpm(rpm);                                                                                                // ver0.31 | if (setfdcmode(fdc.us, type, rpm) != SUCCESS) { | 
|  | return(0); | 
|  | } | 
 | if (biosfd_seek(0, 0)) { | if (biosfd_seek(0, 0)) { | 
 | return(0); | return(0); | 
 | } | } | 
| Line 868  static UINT16 boot_fd1(BYTE rpm) { | Line 737  static UINT16 boot_fd1(BYTE rpm) { | 
 | return(bootseg); | return(bootseg); | 
 | } | } | 
 |  |  | 
| static UINT16 boot_fd(BYTE drv, BYTE type) {                                            // ver0.27 | static UINT16 boot_fd(REG8 drv, REG8 type) {                                            // ver0.27 | 
 |  |  | 
 | UINT16  bootseg; | UINT16  bootseg; | 
 |  |  | 
 | if (drv >= 4) { | if (drv >= 4) { | 
 | return(0); | return(0); | 
 | } | } | 
| fdc.us = drv & 3; | fdc.us = drv; | 
 | if (!fdd_diskready(fdc.us)) { | if (!fdd_diskready(fdc.us)) { | 
 | return(0); | return(0); | 
 | } | } | 
 |  |  | 
 | // 2HD | // 2HD | 
 | if (type & 1) { | if (type & 1) { | 
 | CTRL_FDMEDIA = DISKTYPE_2HD; |  | 
 | // 1.25MB | // 1.25MB | 
| bootseg = boot_fd1(0); | bootseg = boot_fd1(3, 0); | 
 | if (bootseg) { | if (bootseg) { | 
| mem[MEMB_DISK_BOOT] = (BYTE)(0x90+drv); | mem[MEMB_DISK_BOOT] = (UINT8)(0x90 + drv); | 
|  | fddbios_equip(3, TRUE); | 
 | return(bootseg); | return(bootseg); | 
 | } | } | 
 | // 1.44MB | // 1.44MB | 
| bootseg = boot_fd1(1); | bootseg = boot_fd1(3, 1); | 
 | if (bootseg) { | if (bootseg) { | 
| mem[MEMB_DISK_BOOT] = (BYTE)(0x30+drv); | mem[MEMB_DISK_BOOT] = (UINT8)(0x30 + drv); | 
|  | fddbios_equip(3, TRUE); | 
 | return(bootseg); | return(bootseg); | 
 | } | } | 
 | } | } | 
 | if (type & 2) {                                                                         // ver0.29 | if (type & 2) {                                                                         // ver0.29 | 
 | // 2DD | // 2DD | 
| CTRL_FDMEDIA = DISKTYPE_2DD; | bootseg = boot_fd1(0, 0); | 
| bootseg = boot_fd1(0); |  | 
 | if (bootseg) { | if (bootseg) { | 
| mem[MEMB_DISK_BOOT] = (BYTE)(0x70+drv); | mem[MEMB_DISK_BOOT] = (BYTE)(0x70 + drv); | 
| fdmode = 3; | fddbios_equip(0, TRUE); | 
 | return(bootseg); | return(bootseg); | 
 | } | } | 
 | } | } | 
 | return(0); | return(0); | 
 | } | } | 
 |  |  | 
| static UINT16 boot_hd(BYTE drv) {                                                                       // ver0.27 | static REG16 boot_hd(REG8 drv) { | 
 |  |  | 
| BYTE    ret; | REG8    ret; | 
 |  |  | 
 | ret = sxsi_read(drv, 0, mem + 0x1fc00, 0x400); | ret = sxsi_read(drv, 0, mem + 0x1fc00, 0x400); | 
 | if (ret < 0x20) { | if (ret < 0x20) { | 
| Line 921  static UINT16 boot_hd(BYTE drv) { | Line 790  static UINT16 boot_hd(BYTE drv) { | 
 | return(0); | return(0); | 
 | } | } | 
 |  |  | 
| UINT16 bootstrapload(void) {                                                                            // ver0.27 | REG16 bootstrapload(void) { | 
 |  |  | 
 | BYTE    i; | BYTE    i; | 
| UINT16  bootseg; | REG16   bootseg; | 
 |  |  | 
| fdmode = 0; | //      fdmode = 0; | 
 | bootseg = 0; | bootseg = 0; | 
 | switch(mem[MEMB_MSW5] & 0xf0) {         // うぐぅ…本当はALレジスタの値から | switch(mem[MEMB_MSW5] & 0xf0) {         // うぐぅ…本当はALレジスタの値から | 
 | case 0x00:                                      // ノーマル | case 0x00:                                      // ノーマル | 
 | break; | break; | 
 |  |  | 
 | case 0x20:                                      // 640KB FDD | case 0x20:                                      // 640KB FDD | 
 | for (i=0; (i<4) && (!bootseg); i++) { | for (i=0; (i<4) && (!bootseg); i++) { | 
 | if (fdd_diskready(i)) { | if (fdd_diskready(i)) { | 
| Line 938  UINT16 bootstrapload(void) {          // | Line 808  UINT16 bootstrapload(void) {          // | 
 | } | } | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | case 0x40:                                      // 1.2MB FDD | case 0x40:                                      // 1.2MB FDD | 
 | for (i=0; (i<4) && (!bootseg); i++) { | for (i=0; (i<4) && (!bootseg); i++) { | 
 | if (fdd_diskready(i)) { | if (fdd_diskready(i)) { | 
| Line 945  UINT16 bootstrapload(void) {          // | Line 816  UINT16 bootstrapload(void) {          // | 
 | } | } | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | case 0x60:                                      // MO | case 0x60:                                      // MO | 
 | break; | break; | 
 |  |  | 
 | case 0xa0:                                      // SASI 1 | case 0xa0:                                      // SASI 1 | 
| if (sxsi_hd[0].fname[0]) { | bootseg = boot_hd(0x80); | 
| bootseg = boot_hd(0x80); |  | 
| } |  | 
 | break; | break; | 
 |  |  | 
 | case 0xb0:                                      // SASI 2 | case 0xb0:                                      // SASI 2 | 
| if (sxsi_hd[1].fname[0]) { | bootseg = boot_hd(0x81); | 
| bootseg = boot_hd(0x81); |  | 
| } |  | 
 | break; | break; | 
 |  |  | 
 | case 0xc0:                                      // SCSI | case 0xc0:                                      // SCSI | 
| for (i=0; (i<2) && (!bootseg); i++) { | for (i=0; (i<4) && (!bootseg); i++) { | 
| if (sxsi_hd[i+2].fname[0]) { | bootseg = boot_hd((REG8)(0xa0 + i)); | 
| bootseg = boot_hd((BYTE)(0xa0 | i)); |  | 
| } |  | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | default:                                        // ROM | default:                                        // ROM | 
 | return(0); | return(0); | 
 | } | } | 
| Line 973  UINT16 bootstrapload(void) {          // | Line 843  UINT16 bootstrapload(void) {          // | 
 | } | } | 
 | } | } | 
 | for (i=0; (i<2) && (!bootseg); i++) { | for (i=0; (i<2) && (!bootseg); i++) { | 
| if (sxsi_hd[i].fname[0]) { | bootseg = boot_hd((REG8)(0x80 + i)); | 
| bootseg = boot_hd((BYTE)(0x80 | i)); |  | 
| } |  | 
 | } | } | 
| for (i=0; (i<2) && (!bootseg); i++) { | for (i=0; (i<4) && (!bootseg); i++) { | 
| if (sxsi_hd[i+2].fname[0]) { | bootseg = boot_hd((REG8)(0xa0 + i)); | 
| bootseg = boot_hd((BYTE)(0xa0 | i)); |  | 
| } |  | 
 | } | } | 
 |  |  | 
 | init_fdd_equip(); |  | 
 | init_sasi_equip(); |  | 
 | init_scsi_equip(); |  | 
 | return(bootseg); | return(bootseg); | 
 | } | } | 
 |  |  | 
 |  |  | 
 | // -------------------------------------------------------------------------- | // -------------------------------------------------------------------------- | 
 |  |  | 
 | void bios0x1b(void) { | void bios0x1b(void) { | 
 |  |  | 
| BYTE    ret_ah; | REG8    ret_ah; | 
| BYTE    flag; | REG8    flag; | 
|  |  | 
|  | #if defined(SUPPORT_SCSI) | 
|  | if ((CPU_AL & 0xf0) == 0xc0) { | 
|  | TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x", | 
|  | MEML_READ16(CPU_SS, CPU_SP+2), | 
|  | MEML_READ16(CPU_SS, CPU_SP), | 
|  | CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP)); | 
|  | scsicmd_bios(); | 
|  | return; | 
|  | } | 
|  | #endif | 
|  |  | 
|  | #if 1                   // bypass to disk bios | 
|  | { | 
|  | REG8    seg; | 
|  | UINT    sp; | 
|  |  | 
|  | seg = mem[0x004b0 + (CPU_AL >> 4)]; | 
|  | if (seg) { | 
|  | sp = CPU_SP; | 
|  | MEML_WRITE16(CPU_SS, sp - 2, CPU_DS); | 
|  | MEML_WRITE16(CPU_SS, sp - 4, CPU_SI); | 
|  | MEML_WRITE16(CPU_SS, sp - 6, CPU_DI); | 
|  | MEML_WRITE16(CPU_SS, sp - 8, CPU_ES);           // +a | 
|  | MEML_WRITE16(CPU_SS, sp - 10, CPU_BP);          // +8 | 
|  | MEML_WRITE16(CPU_SS, sp - 12, CPU_DX);          // +6 | 
|  | MEML_WRITE16(CPU_SS, sp - 14, CPU_CX);          // +4 | 
|  | MEML_WRITE16(CPU_SS, sp - 16, CPU_BX);          // +2 | 
|  | MEML_WRITE16(CPU_SS, sp - 18, CPU_AX);          // +0 | 
|  | #if 0 | 
|  | TRACEOUT(("call by %.4x:%.4x", | 
|  | MEML_READ16(CPU_SS, CPU_SP+2), | 
|  | MEML_READ16(CPU_SS, CPU_SP))); | 
|  | TRACEOUT(("bypass to %.4x:0018", seg << 8)); | 
|  | TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x", | 
|  | CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, | 
|  | CPU_ES, CPU_BP)); | 
|  | #endif | 
|  | sp -= 18; | 
|  | CPU_SP = sp; | 
|  | CPU_BP = sp; | 
|  | CPU_DS = 0x0000; | 
|  | CPU_BX = 0x04B0; | 
|  | CPU_AX = seg << 8; | 
|  | CPU_CS = seg << 8; | 
|  | CPU_IP = 0x18; | 
|  | return; | 
|  | } | 
|  | } | 
|  | #endif | 
 |  |  | 
| switch(I286_AL & 0xf0) { | switch(CPU_AL & 0xf0) { | 
 | case 0x90: | case 0x90: | 
| ret_ah = fdd_operate(DISKTYPE_2HD, 0, 0); | ret_ah = fdd_operate(3, 0, 0); | 
 | break; | break; | 
 |  |  | 
 | case 0x30: | case 0x30: | 
 | case 0xb0: | case 0xb0: | 
| ret_ah = fdd_operate(DISKTYPE_2HD, 0, 1); | ret_ah = fdd_operate(3, 1, 0); | 
 | break; | break; | 
 |  |  | 
 | case 0x10: | case 0x10: | 
 |  | ret_ah = fdd_operate(1, 0, 0); | 
 |  | break; | 
 |  |  | 
 | case 0x70: | case 0x70: | 
 | case 0xf0: | case 0xf0: | 
| ret_ah = fdd_operate(DISKTYPE_2DD, 0, 0); | ret_ah = fdd_operate(0, 0, 0); | 
 | break; | break; | 
 |  |  | 
 | case 0x50: | case 0x50: | 
| ret_ah = fdd_operate(DISKTYPE_2DD, 1, 0); | ret_ah = fdd_operate(0, 0, 1); | 
 | break; | break; | 
 |  |  | 
 | case 0x00: | case 0x00: | 
 | case 0x80: | case 0x80: | 
| ret_ah = sxsi_operate(HDDTYPE_SASI); | ret_ah = sasibios_operate(); | 
 | break; | break; | 
| #if 0 |  | 
|  | #if defined(SUPPORT_SCSI) | 
 | case 0x20: | case 0x20: | 
 | case 0xa0: | case 0xa0: | 
| ret_ah = sxsi_operate(HDDTYPE_SCSI); | ret_ah = scsibios_operate(); | 
 | break; | break; | 
 | #endif | #endif | 
 |  |  | 
| Line 1032  void bios0x1b(void) { | Line 949  void bios0x1b(void) { | 
 | break; | break; | 
 | } | } | 
 | #if 0 | #if 0 | 
| { | TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n"     \ | 
| static BYTE p = 0; |  | 
| if ((I286_CL == 0x4d) && (ret_ah == 0xe0)) { |  | 
| if (!p) { |  | 
| trace_sw = 1; |  | 
| p++; |  | 
| debug_status(); |  | 
| memorydump(); |  | 
| } |  | 
| } |  | 
| } |  | 
| #endif |  | 
| #if 0 // def TRACE |  | 
| { |  | 
| char    buf[256]; |  | 
| wsprintf(buf, "%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \ |  | 
 | "ES=%04x BP=%04x \nret=%02x", | "ES=%04x BP=%04x \nret=%02x", | 
| i286_memword_read(I286_SS, I286_SP+2), | MEML_READ16(CPU_SS, CPU_SP+2), | 
| i286_memword_read(I286_SS, I286_SP), | MEML_READ16(CPU_SS, CPU_SP), | 
| I286_AX, I286_BX, I286_CL, I286_DH, I286_DL, I286_CH, | CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, | 
| I286_ES, I286_BP, ret_ah); | CPU_ES, CPU_BP, ret_ah)); | 
| TRACE_(buf, 0); |  | 
| } |  | 
 | #endif | #endif | 
| I286_AH = ret_ah; | CPU_AH = ret_ah; | 
| flag = i286_membyte_read(I286_SS, I286_SP+4) & 0xfe; | flag = MEML_READ8(CPU_SS, CPU_SP+4) & 0xfe; | 
 | if (ret_ah >= 0x20) { | if (ret_ah >= 0x20) { | 
| flag |= 1; | flag += 1; | 
 | } | } | 
| i286_membyte_write(I286_SS, I286_SP+4, flag); | MEML_WRITE8(CPU_SS, CPU_SP + 4, flag); | 
 | } | } | 
 |  |  |