np2/bios/bios1b.c - diff

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Diff for /np2/bios/bios1b.c between versions 1.14 and 1.33

version 1.14, 2004/01/23 16:57:20	version 1.33, 2005/05/13 05:46:24
Line 17 enum {	Line 17 enum {
};	};


static BYTE mtr_c = 0;	// ---- FDD
static UINT mtr_r = 0;

	static BOOL setfdcmode(REG8 drv, REG8 type, REG8 rpm) {

// ---- FDD	if (drv >= 4) {
	return(FAILURE);
	}
	if ((rpm) && (!fdc.support144)) {
	return(FAILURE);
	}
	fdc.chgreg = type;
	fdc.rpm[drv] = rpm;
	if (type & 2) {
	CTRL_FDMEDIA = DISKTYPE_2HD;
	}
	else {
	CTRL_FDMEDIA = DISKTYPE_2DD;
	}
	return(SUCCESS);
	}

void fddbios_equip(REG8 type, BOOL clear) {	void fddbios_equip(REG8 type, BOOL clear) {

Line 31 void fddbios_equip(REG8 type, BOOL clear	Line 46 void fddbios_equip(REG8 type, BOOL clear
if (clear) {	if (clear) {
diskequip &= 0x0f00;	diskequip &= 0x0f00;
}	}
if (type == DISKTYPE_2HD) {	if (type & 1) {
diskequip \|= 0x0003;	diskequip &= 0xfff0;
	diskequip \|= (fdc.equip & 0x0f);
}	}
if (type == DISKTYPE_2DD) {	else {
diskequip \|= 0x0300;	diskequip &= 0x0fff;
	diskequip \|= (fdc.equip & 0x0f) << 12;
}	}
SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip);	SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip);
}	}
Line 51 static void biosfd_setchrn(void) {	Line 68 static void biosfd_setchrn(void) {
#if 0	#if 0
static void biosfd_resultout(UINT32 result) {	static void biosfd_resultout(UINT32 result) {

BYTE *ptr;	UINT8 *ptr;

ptr = mem + 0x00564 + (fdc.us*8);	ptr = mem + 0x00564 + (fdc.us*8);
ptr[0] = (BYTE)(result & 0xff) \| (fdc.hd << 2) \| fdc.us;	ptr[0] = (UINT8)(result & 0xff) \| (fdc.hd << 2) \| fdc.us;
ptr[1] = (BYTE)(result >> 8);	ptr[1] = (UINT8)(result >> 8);
ptr[2] = (BYTE)(result >> 16);	ptr[2] = (UINT8)(result >> 16);
ptr[3] = fdc.C;	ptr[3] = fdc.C;
ptr[4] = fdc.H;	ptr[4] = fdc.H;
ptr[5] = fdc.R;	ptr[5] = fdc.R;
Line 76 static BOOL biosfd_seek(REG8 track, BOOL	Line 93 static BOOL biosfd_seek(REG8 track, BOOL
}	}
}	}
fdc.ncn = track;	fdc.ncn = track;
mtr_c = track;
if (fdd_seek()) {	if (fdd_seek()) {
return(FAILURE);	return(FAILURE);
}	}
return(SUCCESS);	return(SUCCESS);
}	}

static UINT16 fdfmt_biospara(REG8 fmt, REG8 rpm) { // ver0.31	static UINT16 fdfmt_biospara(REG8 type, REG8 rpm, REG8 fmt) {

UINT seg;	UINT seg;
UINT off;	UINT off;
Line 93 static UINT16 fdfmt_biospara(REG8 fmt, R	Line 109 static UINT16 fdfmt_biospara(REG8 fmt, R
if (n >= 4) {	if (n >= 4) {
n = 3;	n = 3;
}	}
if (CTRL_FDMEDIA == DISKTYPE_2HD) {	if (type & 2) {
seg = GETBIOSMEM16(MEMW_F2HD_P_SEG);	seg = GETBIOSMEM16(MEMW_F2HD_P_SEG);
off = GETBIOSMEM16(MEMW_F2HD_P_OFF);	off = GETBIOSMEM16(MEMW_F2HD_P_OFF);
}	}
Line 105 static UINT16 fdfmt_biospara(REG8 fmt, R	Line 121 static UINT16 fdfmt_biospara(REG8 fmt, R
off = 0x2361; // see bios.cpp	off = 0x2361; // see bios.cpp
}	}
off += fdc.us * 2;	off += fdc.us * 2;
off = i286_memword_read(seg, off);	off = MEML_READ16(seg, off);
off += n * 8;	off += n * 8;
if (!(CPU_AH & 0x40)) {	if (!(CPU_AH & 0x40)) {
off += 4;	off += 4;
Line 113 static UINT16 fdfmt_biospara(REG8 fmt, R	Line 129 static UINT16 fdfmt_biospara(REG8 fmt, R
if (fmt) {	if (fmt) {
off += 2;	off += 2;
}	}
return(i286_memword_read(seg, off));	return(MEML_READ16(seg, off));
}

static void change_rpm(REG8 rpm) { // ver0.31

if (np2cfg.usefd144) {
fdc.rpm = rpm;
}
}	}



enum {	enum {
FDCBIOS_NORESULT,	FDCBIOS_NORESULT,
FDCBIOS_SUCCESS,	FDCBIOS_SUCCESS,
Line 139 enum {	Line 147 enum {

static void fdd_int(int result) {	static void fdd_int(int result) {

if (result == FDCBIOS_NORESULT) { // ver0.29	if (result == FDCBIOS_NORESULT) {
return;	return;
}	}
switch(CPU_AH & 0x0f) {	switch(CPU_AH & 0x0f) {
Line 152 static void fdd_int(int result) {	Line 160 static void fdd_int(int result) {
case 0x0a: // READ ID	case 0x0a: // READ ID
case 0x0d: // �ե��ޥå�	case 0x0d: // �ե��ޥå�
break;	break;

default:	default:
return;	return;
}	}
Line 188 static void fdd_int(int result) {	Line 197 static void fdd_int(int result) {
fdc.stat[fdc.us] \|= FDCRLT_IC0 \| FDCRLT_NW;	fdc.stat[fdc.us] \|= FDCRLT_IC0 \| FDCRLT_NW;
fdcsend_error7();	fdcsend_error7();
break;	break;

	default:
	return;
	}
	if (fdc.chgreg & 1) {
	mem[MEMB_DISK_INTL] &= ~(0x01 << fdc.us);
	}
	else {
	mem[MEMB_DISK_INTH] &= ~(0x10 << fdc.us);
}	}
	CPU_IP = BIOSOFST_WAIT;
}	}

#if 1	#if 1
Line 261 static void b0clr(void) {	Line 280 static void b0clr(void) {
}	}
#endif	#endif

static REG8 fdd_operate(REG8 type, BOOL ndensity, REG8 rpm) { // ver0.31	static REG8 fdd_operate(REG8 type, REG8 rpm, BOOL ndensity) {

REG8 ret_ah = 0x60;	REG8 ret_ah = 0x60;
UINT16 size;	UINT16 size;
Line 269 static REG8 fdd_operate(REG8 type, BOOL	Line 288 static REG8 fdd_operate(REG8 type, BOOL
UINT16 accesssize;	UINT16 accesssize;
UINT16 secsize;	UINT16 secsize;
UINT16 para;	UINT16 para;
BYTE s;	UINT8 s;
BYTE ID[4];	UINT8 ID[4];
BYTE hd;	UINT8 hd;
int result = FDCBIOS_NORESULT;	int result = FDCBIOS_NORESULT;
UINT32 addr;	UINT32 addr;
	UINT8 mtr_c;
	UINT mtr_r;
	UINT fmode;

mtr_c = 0xff;	mtr_c = fdc.ncn;
mtr_r = 0;	mtr_r = 0;


// �Ȥꤢ��BIOS�λ��̵�뤹��	// �Ȥꤢ��BIOS�λ��̵�뤹��
fdc.mf = 0xff; // ver0.29	fdc.mf = 0xff;

// TRACE_("int 1Bh", CPU_AH);	// TRACE_("int 1Bh", CPU_AH);

change_rpm(rpm); // ver0.31	if (setfdcmode((REG8)(CPU_AL & 3), type, rpm) != SUCCESS) {
	return(0x40);
	}

if ((CPU_AH & 0x0f) != 0x0a) {	if ((CPU_AH & 0x0f) != 0x0a) {
fdc.crcn = 0;	fdc.crcn = 0;
}	}
if ((CPU_AH & 0x0f) != 0x03) {	if ((CPU_AH & 0x0f) != 0x03) {
CTRL_FDMEDIA = type;	if (type & 2) {
switch(type) {	if (pic.pi[1].imr & PIC_INT42) {
case DISKTYPE_2HD:	return(0x40);
if (pic.pi[1].imr & PIC_INT42) {	}
return(0xd0);	}
}	else {
break;	if (pic.pi[1].imr & PIC_INT41) {
case DISKTYPE_2DD:	return(0x40);
if (pic.pi[1].imr & PIC_INT41) {	}
return(0xd0);
}
break;
}	}
if (fdc.us != (CPU_AL & 0x03)) {	if (fdc.us != (CPU_AL & 0x03)) {
fdc.us = CPU_AL & 0x03;	fdc.us = CPU_AL & 0x03;
Line 313 static REG8 fdd_operate(REG8 type, BOOL	Line 334 static REG8 fdd_operate(REG8 type, BOOL
}	}
if (!fdd_diskready(fdc.us)) {	if (!fdd_diskready(fdc.us)) {
fdd_int(FDCBIOS_NONREADY);	fdd_int(FDCBIOS_NONREADY);
if (CPU_AH == 0x84) { // ver0.28	ret_ah = 0x60;
return(0x68); // ��󥹤� ξ�ѥɥ饤�־��	if ((CPU_AX & 0x8f40) == 0x8400) {
}	ret_ah \|= 8; // 1MB/640KBξ�ѥɥ饤��
if (CPU_AH == 0xc4) { // ver0.31	if ((CPU_AH & 0x40) && (fdc.support144)) {
if (np2cfg.usefd144) {	ret_ah \|= 4; // 1.44�б��ɥ饤��
return(0x6c);
}	}
return(0x68);
}	}
return(0x60);	return(ret_ah);
}	}
}	}

// 2DD�Υ⡼�� // ver0.29	// �⡼�� // ver0.78
if (type == DISKTYPE_2DD) {	fmode = (type & 1)?MEMB_F2HD_MODE:MEMB_F2DD_MODE;
if (!(mem[MEMB_F2DD_MODE] & (0x10 << fdc.us))) {	if (!(CPU_AL & 0x80)) {
ndensity = 1;	if (!(mem[fmode] & (0x10 << fdc.us))) {
	ndensity = TRUE;
}	}
}	}

Line 358 static REG8 fdd_operate(REG8 type, BOOL	Line 378 static REG8 fdd_operate(REG8 type, BOOL
}	}
}	}
biosfd_setchrn();	biosfd_setchrn();
para = fdfmt_biospara(0, rpm);	para = fdfmt_biospara(type, rpm, 0);
if (!para) {	if (!para) {
ret_ah = 0xd0;	ret_ah = 0xd0;
break;	break;
Line 381 static REG8 fdd_operate(REG8 type, BOOL	Line 401 static REG8 fdd_operate(REG8 type, BOOL
break;	break;
}	}
size -= accesssize;	size -= accesssize;
mtr_r += accesssize; // ver0.26	mtr_r += accesssize;
if ((fdc.R++ == (UINT8)para) &&	if ((fdc.R++ == (UINT8)para) &&
(CPU_AH & 0x80) && (!fdc.hd)) {	(CPU_AH & 0x80) && (!fdc.hd)) {
fdc.hd = 1;	fdc.hd = 1;
Line 419 static REG8 fdd_operate(REG8 type, BOOL	Line 439 static REG8 fdd_operate(REG8 type, BOOL
ret_ah \|= 0x01;	ret_ah \|= 0x01;
}	}
else { // 2DD	else { // 2DD
if (mem[0x005ca] & (0x01 << fdc.us)) {	if (mem[fmode] & (0x01 << fdc.us)) {
ret_ah++;	ret_ah \|= 0x01;
}	}
if (mem[0x005ca] & (0x10 << fdc.us)) { // ver0.30	if (mem[fmode] & (0x10 << fdc.us)) {
ret_ah \|= 0x04;	ret_ah \|= 0x04;
}	}
}	}
if (CPU_AH & 0x80) { // ver0.30	if ((CPU_AX & 0x8f40) == 0x8400) {
ret_ah \|= 8; // 1MB/640KBξ�ѥɥ饤��	ret_ah \|= 8; // 1MB/640KBξ�ѥɥ饤��
if ((CPU_AH & 0x40) &&	if ((CPU_AH & 0x40) && (fdc.support144)) {
(np2cfg.usefd144)) { // ver0.31
ret_ah \|= 4; // 1.44�б��ɥ饤��	ret_ah \|= 4; // 1.44�б��ɥ饤��
}	}
}	}
Line 447 static REG8 fdd_operate(REG8 type, BOOL	Line 466 static REG8 fdd_operate(REG8 type, BOOL
}	}
}	}
biosfd_setchrn();	biosfd_setchrn();
para = fdfmt_biospara(0, rpm);	para = fdfmt_biospara(type, rpm, 0);
if (!para) {	if (!para) {
ret_ah = 0xd0;	ret_ah = 0xd0;
break;	break;
Line 472 static REG8 fdd_operate(REG8 type, BOOL	Line 491 static REG8 fdd_operate(REG8 type, BOOL
else {	else {
accesssize = size;	accesssize = size;
}	}
i286_memx_read(addr, fdc.buf, accesssize);	MEML_READ(addr, fdc.buf, accesssize);
if (fdd_write()) {	if (fdd_write()) {
break;	break;
}	}
addr += accesssize;	addr += accesssize;
size -= accesssize;	size -= accesssize;
mtr_r += accesssize; // ver0.26	mtr_r += accesssize;
if ((fdc.R++ == (UINT8)para) &&	if ((fdc.R++ == (UINT8)para) &&
(CPU_AH & 0x80) && (!fdc.hd)) {	(CPU_AH & 0x80) && (!fdc.hd)) {
fdc.hd = 1;	fdc.hd = 1;
Line 494 static REG8 fdd_operate(REG8 type, BOOL	Line 513 static REG8 fdd_operate(REG8 type, BOOL
result = FDCBIOS_SUCCESS;	result = FDCBIOS_SUCCESS;
}	}
else {	else {
ret_ah = fddlasterror; // 0xc0 // ver0.28	ret_ah = fddlasterror; // 0xc0
result = FDCBIOS_WRITEERROR;	result = FDCBIOS_WRITEERROR;
}	}
break;	break;
Line 512 static REG8 fdd_operate(REG8 type, BOOL	Line 531 static REG8 fdd_operate(REG8 type, BOOL
}	}
}	}
biosfd_setchrn();	biosfd_setchrn();
para = fdfmt_biospara(0, rpm);	para = fdfmt_biospara(type, rpm, 0);
if (!para) {	if (!para) {
ret_ah = 0xd0;	ret_ah = 0xd0;
break;	break;
Line 541 static REG8 fdd_operate(REG8 type, BOOL	Line 560 static REG8 fdd_operate(REG8 type, BOOL
if (fdd_read()) {	if (fdd_read()) {
break;	break;
}	}
i286_memx_write(addr, fdc.buf, accesssize);	MEML_WRITE(addr, fdc.buf, accesssize);
addr += accesssize;	addr += accesssize;
size -= accesssize;	size -= accesssize;
mtr_r += accesssize; // ver0.26	mtr_r += accesssize;
if (fdc.R++ == (UINT8)para) {	if (fdc.R++ == (UINT8)para) {
if ((CPU_AH & 0x80) && (!fdc.hd)) {	if ((CPU_AH & 0x80) && (!fdc.hd)) {
fdc.hd = 1;	fdc.hd = 1;
Line 582 static REG8 fdd_operate(REG8 type, BOOL	Line 601 static REG8 fdd_operate(REG8 type, BOOL
}	}
#endif	#endif
else {	else {
ret_ah = fddlasterror; // 0xc0; // ver0.28	ret_ah = fddlasterror; // 0xc0;
result = FDCBIOS_READERROR;	result = FDCBIOS_READERROR;
}	}
break;	break;
Line 594 static REG8 fdd_operate(REG8 type, BOOL	Line 613 static REG8 fdd_operate(REG8 type, BOOL
break;	break;

case 0x0a: // READ ID	case 0x0a: // READ ID
fdc.mf = CPU_AH & 0x40; // ver0.29	fdc.mf = CPU_AH & 0x40;
if (CPU_AH & 0x10) { // ver0.28	if (CPU_AH & 0x10) {
if (!biosfd_seek(CPU_CL, ndensity)) {	if (!biosfd_seek(CPU_CL, ndensity)) {
result = FDCBIOS_SEEKSUCCESS;	result = FDCBIOS_SEEKSUCCESS;
}	}
Line 606 static REG8 fdd_operate(REG8 type, BOOL	Line 625 static REG8 fdd_operate(REG8 type, BOOL
}	}
}	}
if (fdd_readid()) {	if (fdd_readid()) {
ret_ah = fddlasterror; // 0xa0; // ver0.28	ret_ah = fddlasterror; // 0xa0;
break;	break;
}	}
if (fdc.N < 8) { // ver0.26	if (fdc.N < 8) {
mtr_r += 128 << fdc.N;	mtr_r += 128 << fdc.N;
}	}
else {	else {
Line 633 static REG8 fdd_operate(REG8 type, BOOL	Line 652 static REG8 fdd_operate(REG8 type, BOOL
}	}
fdc.d = CPU_DL;	fdc.d = CPU_DL;
fdc.N = CPU_CH;	fdc.N = CPU_CH;
para = fdfmt_biospara(1, rpm);	para = fdfmt_biospara(type, rpm, 1);
if (!para) {	if (!para) {
ret_ah = 0xd0;	ret_ah = 0xd0;
break;	break;
Line 642 static REG8 fdd_operate(REG8 type, BOOL	Line 661 static REG8 fdd_operate(REG8 type, BOOL
fdd_formatinit();	fdd_formatinit();
pos = CPU_BP;	pos = CPU_BP;
for (s=0; s<fdc.sc; s++) {	for (s=0; s<fdc.sc; s++) {
i286_memstr_read(CPU_ES, pos, ID, 4);	MEML_READSTR(CPU_ES, pos, ID, 4);
fdd_formating(ID);	fdd_formating(ID);
pos += 4;	pos += 4;
	if (ID[3] < 8) {
	mtr_r += 128 << ID[3];
	}
	else {
	mtr_r += 128 << 8;
	}
	}
	ret_ah = 0x00;
	break;

	case 0x0e: // ver0.78
	if (CPU_AH & 0x80) { // ̩��
	mem[fmode] &= 0x0f;
	mem[fmode] \|= (UINT8)((CPU_AH & 0x0f) << 4);
	}
	else { // ��
	mem[fmode] &= 0xf0;
	mem[fmode] \|= (UINT8)(CPU_AH & 0x0f);
}	}
ret_ah = 0x00;	ret_ah = 0x00;
break;	break;
}	}
fdd_int(result);	fdd_int(result);
fddmtr_seek(fdc.us, mtr_c, mtr_r);	if (mtr_c != fdc.ncn) {
CPU_IP = BIOSOFST_WAIT; // ver0.30	fddmtr_seek(fdc.us, mtr_c, mtr_r);
	}
return(ret_ah);	return(ret_ah);
}	}


// -------------------------------------------------------------------- BIOS	// -------------------------------------------------------------------- BIOS

static UINT16 boot_fd1(REG8 rpm) { // ver0.31	static UINT16 boot_fd1(REG8 type, REG8 rpm) {

UINT remain;	UINT remain;
UINT size;	UINT size;
UINT32 pos;	UINT32 pos;
UINT16 bootseg;	UINT16 bootseg;

change_rpm(rpm); // ver0.31	if (setfdcmode(fdc.us, type, rpm) != SUCCESS) {
	return(0);
	}
if (biosfd_seek(0, 0)) {	if (biosfd_seek(0, 0)) {
return(0);	return(0);
}	}
Line 709 static UINT16 boot_fd1(REG8 rpm) {	Line 749 static UINT16 boot_fd1(REG8 rpm) {
return(bootseg);	return(bootseg);
}	}

static UINT16 boot_fd(REG8 drv, REG8 type) { // ver0.27	static UINT16 boot_fd(REG8 drv, REG8 type) {

UINT16 bootseg;	UINT16 bootseg;

if (drv >= 4) {	if (drv >= 4) {
return(0);	return(0);
}	}
fdc.us = drv & 3;	fdc.us = drv;
if (!fdd_diskready(fdc.us)) {	if (!fdd_diskready(fdc.us)) {
return(0);	return(0);
}	}

// 2HD	// 2HD
if (type & 1) {	if (type & 1) {
CTRL_FDMEDIA = DISKTYPE_2HD;
// 1.25MB	// 1.25MB
bootseg = boot_fd1(0);	bootseg = boot_fd1(3, 0);
if (bootseg) {	if (bootseg) {
mem[MEMB_DISK_BOOT] = (UINT8)(0x90 + drv);	mem[MEMB_DISK_BOOT] = (UINT8)(0x90 + drv);
fddbios_equip(DISKTYPE_2HD, TRUE);	fddbios_equip(3, TRUE);
return(bootseg);	return(bootseg);
}	}
// 1.44MB	// 1.44MB
bootseg = boot_fd1(1);	bootseg = boot_fd1(3, 1);
if (bootseg) {	if (bootseg) {
mem[MEMB_DISK_BOOT] = (UINT8)(0x30 + drv);	mem[MEMB_DISK_BOOT] = (UINT8)(0x30 + drv);
fddbios_equip(DISKTYPE_2HD, TRUE);	fddbios_equip(3, TRUE);
return(bootseg);	return(bootseg);
}	}
}	}
if (type & 2) { // ver0.29	if (type & 2) {
// 2DD	// 2DD
CTRL_FDMEDIA = DISKTYPE_2DD;	bootseg = boot_fd1(0, 0);
bootseg = boot_fd1(0);
if (bootseg) {	if (bootseg) {
mem[MEMB_DISK_BOOT] = (BYTE)(0x70 + drv);	mem[MEMB_DISK_BOOT] = (UINT8)(0x70 + drv);
fddbios_equip(DISKTYPE_2DD, TRUE);	fddbios_equip(0, TRUE);
return(bootseg);	return(bootseg);
}	}
}	}
Line 766 static REG16 boot_hd(REG8 drv) {	Line 804 static REG16 boot_hd(REG8 drv) {

REG16 bootstrapload(void) {	REG16 bootstrapload(void) {

BYTE i;	UINT8 i;
REG16 bootseg;	REG16 bootseg;

// fdmode = 0;	// fdmode = 0;
Line 833 void bios0x1b(void) {	Line 871 void bios0x1b(void) {
REG8 ret_ah;	REG8 ret_ah;
REG8 flag;	REG8 flag;

#if defined(SUPPORT_SCSI)
if ((CPU_AL & 0xf0) == 0xc0) {
TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x",
i286_memword_read(CPU_SS, CPU_SP+2),
i286_memword_read(CPU_SS, CPU_SP),
CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP));
scsicmd_bios();
return;
}
#endif

#if 1 // bypass to disk bios	#if 1 // bypass to disk bios
{
REG8 seg;	REG8 seg;
UINT sp;	UINT sp;

seg = mem[0x004b0 + (CPU_AL >> 4)];	seg = mem[MEMX_DISK_XROM + (CPU_AL >> 4)];
if (seg) {	if (seg) {
TRACEOUT(("call by %.4x:%.4x",
i286_memword_read(CPU_SS, CPU_SP+2),
i286_memword_read(CPU_SS, CPU_SP)));
sp = CPU_SP;	sp = CPU_SP;
i286_memword_write(CPU_SS, sp - 2, CPU_DS);	MEML_WRITE16(CPU_SS, sp - 2, CPU_DS);
i286_memword_write(CPU_SS, sp - 4, CPU_SI);	MEML_WRITE16(CPU_SS, sp - 4, CPU_SI);
i286_memword_write(CPU_SS, sp - 6, CPU_DI);	MEML_WRITE16(CPU_SS, sp - 6, CPU_DI);
i286_memword_write(CPU_SS, sp - 8, CPU_ES); // +a	MEML_WRITE16(CPU_SS, sp - 8, CPU_ES); // +a
i286_memword_write(CPU_SS, sp - 10, CPU_BP); // +8	MEML_WRITE16(CPU_SS, sp - 10, CPU_BP); // +8
i286_memword_write(CPU_SS, sp - 12, CPU_DX); // +6	MEML_WRITE16(CPU_SS, sp - 12, CPU_DX); // +6
i286_memword_write(CPU_SS, sp - 14, CPU_CX); // +4	MEML_WRITE16(CPU_SS, sp - 14, CPU_CX); // +4
i286_memword_write(CPU_SS, sp - 16, CPU_BX); // +2	MEML_WRITE16(CPU_SS, sp - 16, CPU_BX); // +2
i286_memword_write(CPU_SS, sp - 18, CPU_AX); // +0	MEML_WRITE16(CPU_SS, sp - 18, CPU_AX); // +0
	#if 0
	TRACEOUT(("call by %.4x:%.4x",
	MEML_READ16(CPU_SS, CPU_SP+2),
	MEML_READ16(CPU_SS, CPU_SP)));
TRACEOUT(("bypass to %.4x:0018", seg << 8));	TRACEOUT(("bypass to %.4x:0018", seg << 8));
TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x",	TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x",
CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,	CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,
CPU_ES, CPU_BP));	CPU_ES, CPU_BP));
	#endif
sp -= 18;	sp -= 18;
CPU_SP = sp;	CPU_SP = sp;
CPU_BP = sp;	CPU_BP = sp;
Line 878 void bios0x1b(void) {	Line 906 void bios0x1b(void) {
CPU_IP = 0x18;	CPU_IP = 0x18;
return;	return;
}	}
}	#endif

	#if defined(SUPPORT_SCSI)
	if ((CPU_AL & 0xf0) == 0xc0) {
	TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x",
	MEML_READ16(CPU_SS, CPU_SP+2),
	MEML_READ16(CPU_SS, CPU_SP),
	CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP));
	scsicmd_bios();
	return;
	}
#endif	#endif

switch(CPU_AL & 0xf0) {	switch(CPU_AL & 0xf0) {
case 0x90:	case 0x90:
ret_ah = fdd_operate(DISKTYPE_2HD, 0, 0);	ret_ah = fdd_operate(3, 0, FALSE);
break;	break;

case 0x30:	case 0x30:
case 0xb0:	case 0xb0:
ret_ah = fdd_operate(DISKTYPE_2HD, 0, 1);	ret_ah = fdd_operate(3, 1, FALSE);
break;	break;

case 0x10:	case 0x10:
	ret_ah = fdd_operate(1, 0, FALSE);
	break;

case 0x70:	case 0x70:
case 0xf0:	case 0xf0:
ret_ah = fdd_operate(DISKTYPE_2DD, 0, 0);	ret_ah = fdd_operate(0, 0, FALSE);
break;	break;

case 0x50:	case 0x50:
ret_ah = fdd_operate(DISKTYPE_2DD, 1, 0);	ret_ah = fdd_operate(0, 0, TRUE);
break;	break;

case 0x00:	case 0x00:
Line 920 void bios0x1b(void) {	Line 961 void bios0x1b(void) {
#if 0	#if 0
TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \	TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \
"ES=%04x BP=%04x \nret=%02x",	"ES=%04x BP=%04x \nret=%02x",
i286_memword_read(CPU_SS, CPU_SP+2),	MEML_READ16(CPU_SS, CPU_SP+2),
i286_memword_read(CPU_SS, CPU_SP),	MEML_READ16(CPU_SS, CPU_SP),
CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,	CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,
CPU_ES, CPU_BP, ret_ah));	CPU_ES, CPU_BP, ret_ah));
#endif	#endif
CPU_AH = ret_ah;	CPU_AH = ret_ah;
flag = i286_membyte_read(CPU_SS, CPU_SP+4) & 0xfe;	flag = MEML_READ8(CPU_SS, CPU_SP+4) & 0xfe;
if (ret_ah >= 0x20) {	if (ret_ah >= 0x20) {
flag += 1;	flag += 1;
}	}
i286_membyte_write(CPU_SS, CPU_SP + 4, flag);	MEML_WRITE8(CPU_SS, CPU_SP + 4, flag);
	}

	UINT bios0x1b_wait(void) {

	UINT addr;
	REG8 bit;

	if (fddmtr.busy) {
	CPU_IP--;
	CPU_REMCLOCK = -1;
	}
	else {
	if (fdc.chgreg & 1) {
	addr = MEMB_DISK_INTL;
	bit = 0x01;
	}
	else {
	addr = MEMB_DISK_INTH;
	bit = 0x10;
	}
	bit <<= fdc.us;
	if (mem[addr] & bit) {
	mem[addr] &= ~bit;
	return(0);
	}
	else {
	CPU_REMCLOCK -= 1000;
	}
	}
	CPU_IP--;
	return(1);
}	}

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.14
changed lines
	Added in v.1.33