np2/bios/bios1b.c - diff

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Diff for /np2/bios/bios1b.c between versions 1.25 and 1.33

version 1.25, 2004/03/07 23:04:50	version 1.33, 2005/05/13 05:46:24
Line 68 static void biosfd_setchrn(void) {	Line 68 static void biosfd_setchrn(void) {
#if 0	#if 0
static void biosfd_resultout(UINT32 result) {	static void biosfd_resultout(UINT32 result) {

BYTE *ptr;	UINT8 *ptr;

ptr = mem + 0x00564 + (fdc.us*8);	ptr = mem + 0x00564 + (fdc.us*8);
ptr[0] = (BYTE)(result & 0xff) \| (fdc.hd << 2) \| fdc.us;	ptr[0] = (UINT8)(result & 0xff) \| (fdc.hd << 2) \| fdc.us;
ptr[1] = (BYTE)(result >> 8);	ptr[1] = (UINT8)(result >> 8);
ptr[2] = (BYTE)(result >> 16);	ptr[2] = (UINT8)(result >> 16);
ptr[3] = fdc.C;	ptr[3] = fdc.C;
ptr[4] = fdc.H;	ptr[4] = fdc.H;
ptr[5] = fdc.R;	ptr[5] = fdc.R;
Line 147 enum {	Line 147 enum {

static void fdd_int(int result) {	static void fdd_int(int result) {

if (result == FDCBIOS_NORESULT) { // ver0.29	if (result == FDCBIOS_NORESULT) {
return;	return;
}	}
switch(CPU_AH & 0x0f) {	switch(CPU_AH & 0x0f) {
Line 202 static void fdd_int(int result) {	Line 202 static void fdd_int(int result) {
return;	return;
}	}
if (fdc.chgreg & 1) {	if (fdc.chgreg & 1) {
mem[0x0055e] &= ~(0x01 << fdc.us);	mem[MEMB_DISK_INTL] &= ~(0x01 << fdc.us);
}	}
else {	else {
mem[0x0055f] &= ~(0x10 << fdc.us);	mem[MEMB_DISK_INTH] &= ~(0x10 << fdc.us);
}	}
CPU_IP = BIOSOFST_WAIT;	CPU_IP = BIOSOFST_WAIT;
}	}
Line 288 static REG8 fdd_operate(REG8 type, REG8	Line 288 static REG8 fdd_operate(REG8 type, REG8
UINT16 accesssize;	UINT16 accesssize;
UINT16 secsize;	UINT16 secsize;
UINT16 para;	UINT16 para;
BYTE s;	UINT8 s;
BYTE ID[4];	UINT8 ID[4];
BYTE hd;	UINT8 hd;
int result = FDCBIOS_NORESULT;	int result = FDCBIOS_NORESULT;
UINT32 addr;	UINT32 addr;
UINT8 mtr_c;	UINT8 mtr_c;
UINT mtr_r;	UINT mtr_r;
	UINT fmode;

mtr_c = fdc.ncn;	mtr_c = fdc.ncn;
mtr_r = 0;	mtr_r = 0;

// とりあえずBIOSの時は無視する	// とりあえずBIOSの時は無視する
fdc.mf = 0xff; // ver0.29	fdc.mf = 0xff;

// TRACE_("int 1Bh", CPU_AH);	// TRACE_("int 1Bh", CPU_AH);

Line 333 static REG8 fdd_operate(REG8 type, REG8	Line 334 static REG8 fdd_operate(REG8 type, REG8
}	}
if (!fdd_diskready(fdc.us)) {	if (!fdd_diskready(fdc.us)) {
fdd_int(FDCBIOS_NONREADY);	fdd_int(FDCBIOS_NONREADY);
if (CPU_AH == 0x84) { // ver0.28	ret_ah = 0x60;
return(0x68); // 新センスは両用ドライブ情報も	if ((CPU_AX & 0x8f40) == 0x8400) {
}	ret_ah \|= 8; // 1MB/640KB両用ドライブ
if (CPU_AH == 0xc4) { // ver0.31	if ((CPU_AH & 0x40) && (fdc.support144)) {
if (fdc.support144) {	ret_ah \|= 4; // 1.44対応ドライブ
return(0x6c);
}	}
return(0x68);
}	}
return(0x60);	return(ret_ah);
}	}
}	}

// 2DDのモード選択 // ver0.29	// モード選択 // ver0.78
if (type == DISKTYPE_2DD) {	fmode = (type & 1)?MEMB_F2HD_MODE:MEMB_F2DD_MODE;
if (!(mem[MEMB_F2DD_MODE] & (0x10 << fdc.us))) {	if (!(CPU_AL & 0x80)) {
ndensity = 1;	if (!(mem[fmode] & (0x10 << fdc.us))) {
	ndensity = TRUE;
}	}
}	}

Line 401 static REG8 fdd_operate(REG8 type, REG8	Line 401 static REG8 fdd_operate(REG8 type, REG8
break;	break;
}	}
size -= accesssize;	size -= accesssize;
mtr_r += accesssize; // ver0.26	mtr_r += accesssize;
if ((fdc.R++ == (UINT8)para) &&	if ((fdc.R++ == (UINT8)para) &&
(CPU_AH & 0x80) && (!fdc.hd)) {	(CPU_AH & 0x80) && (!fdc.hd)) {
fdc.hd = 1;	fdc.hd = 1;
Line 439 static REG8 fdd_operate(REG8 type, REG8	Line 439 static REG8 fdd_operate(REG8 type, REG8
ret_ah \|= 0x01;	ret_ah \|= 0x01;
}	}
else { // 2DD	else { // 2DD
if (mem[0x005ca] & (0x01 << fdc.us)) {	if (mem[fmode] & (0x01 << fdc.us)) {
ret_ah++;	ret_ah \|= 0x01;
}	}
if (mem[0x005ca] & (0x10 << fdc.us)) { // ver0.30	if (mem[fmode] & (0x10 << fdc.us)) {
ret_ah \|= 0x04;	ret_ah \|= 0x04;
}	}
}	}
if (CPU_AH & 0x80) { // ver0.30	if ((CPU_AX & 0x8f40) == 0x8400) {
ret_ah \|= 8; // 1MB/640KB両用ドライブ	ret_ah \|= 8; // 1MB/640KB両用ドライブ
if ((CPU_AH & 0x40) && (fdc.support144)) {	if ((CPU_AH & 0x40) && (fdc.support144)) {
ret_ah \|= 4; // 1.44対応ドライブ	ret_ah \|= 4; // 1.44対応ドライブ
Line 497 static REG8 fdd_operate(REG8 type, REG8	Line 497 static REG8 fdd_operate(REG8 type, REG8
}	}
addr += accesssize;	addr += accesssize;
size -= accesssize;	size -= accesssize;
mtr_r += accesssize; // ver0.26	mtr_r += accesssize;
if ((fdc.R++ == (UINT8)para) &&	if ((fdc.R++ == (UINT8)para) &&
(CPU_AH & 0x80) && (!fdc.hd)) {	(CPU_AH & 0x80) && (!fdc.hd)) {
fdc.hd = 1;	fdc.hd = 1;
Line 513 static REG8 fdd_operate(REG8 type, REG8	Line 513 static REG8 fdd_operate(REG8 type, REG8
result = FDCBIOS_SUCCESS;	result = FDCBIOS_SUCCESS;
}	}
else {	else {
ret_ah = fddlasterror; // 0xc0 // ver0.28	ret_ah = fddlasterror; // 0xc0
result = FDCBIOS_WRITEERROR;	result = FDCBIOS_WRITEERROR;
}	}
break;	break;
Line 563 static REG8 fdd_operate(REG8 type, REG8	Line 563 static REG8 fdd_operate(REG8 type, REG8
MEML_WRITE(addr, fdc.buf, accesssize);	MEML_WRITE(addr, fdc.buf, accesssize);
addr += accesssize;	addr += accesssize;
size -= accesssize;	size -= accesssize;
mtr_r += accesssize; // ver0.26	mtr_r += accesssize;
if (fdc.R++ == (UINT8)para) {	if (fdc.R++ == (UINT8)para) {
if ((CPU_AH & 0x80) && (!fdc.hd)) {	if ((CPU_AH & 0x80) && (!fdc.hd)) {
fdc.hd = 1;	fdc.hd = 1;
Line 601 static REG8 fdd_operate(REG8 type, REG8	Line 601 static REG8 fdd_operate(REG8 type, REG8
}	}
#endif	#endif
else {	else {
ret_ah = fddlasterror; // 0xc0; // ver0.28	ret_ah = fddlasterror; // 0xc0;
result = FDCBIOS_READERROR;	result = FDCBIOS_READERROR;
}	}
break;	break;
Line 613 static REG8 fdd_operate(REG8 type, REG8	Line 613 static REG8 fdd_operate(REG8 type, REG8
break;	break;

case 0x0a: // READ ID	case 0x0a: // READ ID
fdc.mf = CPU_AH & 0x40; // ver0.29	fdc.mf = CPU_AH & 0x40;
if (CPU_AH & 0x10) { // ver0.28	if (CPU_AH & 0x10) {
if (!biosfd_seek(CPU_CL, ndensity)) {	if (!biosfd_seek(CPU_CL, ndensity)) {
result = FDCBIOS_SEEKSUCCESS;	result = FDCBIOS_SEEKSUCCESS;
}	}
Line 625 static REG8 fdd_operate(REG8 type, REG8	Line 625 static REG8 fdd_operate(REG8 type, REG8
}	}
}	}
if (fdd_readid()) {	if (fdd_readid()) {
ret_ah = fddlasterror; // 0xa0; // ver0.28	ret_ah = fddlasterror; // 0xa0;
break;	break;
}	}
if (fdc.N < 8) { // ver0.26	if (fdc.N < 8) {
mtr_r += 128 << fdc.N;	mtr_r += 128 << fdc.N;
}	}
else {	else {
Line 673 static REG8 fdd_operate(REG8 type, REG8	Line 673 static REG8 fdd_operate(REG8 type, REG8
}	}
ret_ah = 0x00;	ret_ah = 0x00;
break;	break;

	case 0x0e: // ver0.78
	if (CPU_AH & 0x80) { // 密度設定
	mem[fmode] &= 0x0f;
	mem[fmode] \|= (UINT8)((CPU_AH & 0x0f) << 4);
	}
	else { // 面設定
	mem[fmode] &= 0xf0;
	mem[fmode] \|= (UINT8)(CPU_AH & 0x0f);
	}
	ret_ah = 0x00;
	break;
}	}
fdd_int(result);	fdd_int(result);
if (mtr_c != fdc.ncn) {	if (mtr_c != fdc.ncn) {
Line 737 static UINT16 boot_fd1(REG8 type, REG8 r	Line 749 static UINT16 boot_fd1(REG8 type, REG8 r
return(bootseg);	return(bootseg);
}	}

static UINT16 boot_fd(REG8 drv, REG8 type) { // ver0.27	static UINT16 boot_fd(REG8 drv, REG8 type) {

UINT16 bootseg;	UINT16 bootseg;

Line 766 static UINT16 boot_fd(REG8 drv, REG8 typ	Line 778 static UINT16 boot_fd(REG8 drv, REG8 typ
return(bootseg);	return(bootseg);
}	}
}	}
if (type & 2) { // ver0.29	if (type & 2) {
// 2DD	// 2DD
bootseg = boot_fd1(0, 0);	bootseg = boot_fd1(0, 0);
if (bootseg) {	if (bootseg) {
mem[MEMB_DISK_BOOT] = (BYTE)(0x70 + drv);	mem[MEMB_DISK_BOOT] = (UINT8)(0x70 + drv);
fddbios_equip(0, TRUE);	fddbios_equip(0, TRUE);
return(bootseg);	return(bootseg);
}	}
Line 792 static REG16 boot_hd(REG8 drv) {	Line 804 static REG16 boot_hd(REG8 drv) {

REG16 bootstrapload(void) {	REG16 bootstrapload(void) {

BYTE i;	UINT8 i;
REG16 bootseg;	REG16 bootseg;

// fdmode = 0;	// fdmode = 0;
Line 859 void bios0x1b(void) {	Line 871 void bios0x1b(void) {
REG8 ret_ah;	REG8 ret_ah;
REG8 flag;	REG8 flag;

#if defined(SUPPORT_SCSI)
if ((CPU_AL & 0xf0) == 0xc0) {
TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x",
MEML_READ16(CPU_SS, CPU_SP+2),
MEML_READ16(CPU_SS, CPU_SP),
CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP));
scsicmd_bios();
return;
}
#endif

#if 1 // bypass to disk bios	#if 1 // bypass to disk bios
{
REG8 seg;	REG8 seg;
UINT sp;	UINT sp;

seg = mem[0x004b0 + (CPU_AL >> 4)];	seg = mem[MEMX_DISK_XROM + (CPU_AL >> 4)];
if (seg) {	if (seg) {
TRACEOUT(("call by %.4x:%.4x",
MEML_READ16(CPU_SS, CPU_SP+2),
MEML_READ16(CPU_SS, CPU_SP)));
sp = CPU_SP;	sp = CPU_SP;
MEML_WRITE16(CPU_SS, sp - 2, CPU_DS);	MEML_WRITE16(CPU_SS, sp - 2, CPU_DS);
MEML_WRITE16(CPU_SS, sp - 4, CPU_SI);	MEML_WRITE16(CPU_SS, sp - 4, CPU_SI);
Line 891 void bios0x1b(void) {	Line 888 void bios0x1b(void) {
MEML_WRITE16(CPU_SS, sp - 16, CPU_BX); // +2	MEML_WRITE16(CPU_SS, sp - 16, CPU_BX); // +2
MEML_WRITE16(CPU_SS, sp - 18, CPU_AX); // +0	MEML_WRITE16(CPU_SS, sp - 18, CPU_AX); // +0
#if 0	#if 0
	TRACEOUT(("call by %.4x:%.4x",
	MEML_READ16(CPU_SS, CPU_SP+2),
	MEML_READ16(CPU_SS, CPU_SP)));
TRACEOUT(("bypass to %.4x:0018", seg << 8));	TRACEOUT(("bypass to %.4x:0018", seg << 8));
TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x",	TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x",
CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,	CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,
Line 906 void bios0x1b(void) {	Line 906 void bios0x1b(void) {
CPU_IP = 0x18;	CPU_IP = 0x18;
return;	return;
}	}
}	#endif

	#if defined(SUPPORT_SCSI)
	if ((CPU_AL & 0xf0) == 0xc0) {
	TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x",
	MEML_READ16(CPU_SS, CPU_SP+2),
	MEML_READ16(CPU_SS, CPU_SP),
	CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP));
	scsicmd_bios();
	return;
	}
#endif	#endif

switch(CPU_AL & 0xf0) {	switch(CPU_AL & 0xf0) {
case 0x90:	case 0x90:
ret_ah = fdd_operate(3, 0, 0);	ret_ah = fdd_operate(3, 0, FALSE);
break;	break;

case 0x30:	case 0x30:
case 0xb0:	case 0xb0:
ret_ah = fdd_operate(3, 1, 0);	ret_ah = fdd_operate(3, 1, FALSE);
break;	break;

case 0x10:	case 0x10:
ret_ah = fdd_operate(1, 0, 0);	ret_ah = fdd_operate(1, 0, FALSE);
break;	break;

case 0x70:	case 0x70:
case 0xf0:	case 0xf0:
ret_ah = fdd_operate(0, 0, 0);	ret_ah = fdd_operate(0, 0, FALSE);
break;	break;

case 0x50:	case 0x50:
ret_ah = fdd_operate(0, 0, 1);	ret_ah = fdd_operate(0, 0, TRUE);
break;	break;

case 0x00:	case 0x00:
Line 964 void bios0x1b(void) {	Line 974 void bios0x1b(void) {
MEML_WRITE8(CPU_SS, CPU_SP + 4, flag);	MEML_WRITE8(CPU_SS, CPU_SP + 4, flag);
}	}

	UINT bios0x1b_wait(void) {

	UINT addr;
	REG8 bit;

	if (fddmtr.busy) {
	CPU_IP--;
	CPU_REMCLOCK = -1;
	}
	else {
	if (fdc.chgreg & 1) {
	addr = MEMB_DISK_INTL;
	bit = 0x01;
	}
	else {
	addr = MEMB_DISK_INTH;
	bit = 0x10;
	}
	bit <<= fdc.us;
	if (mem[addr] & bit) {
	mem[addr] &= ~bit;
	return(0);
	}
	else {
	CPU_REMCLOCK -= 1000;
	}
	}
	CPU_IP--;
	return(1);
	}

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.25
changed lines
	Added in v.1.33