--- np2/bios/bios1b.c 2004/01/29 09:41:49 1.16 +++ np2/bios/bios1b.c 2012/01/23 09:59:51 1.37 @@ -17,24 +17,28 @@ enum { }; -static BYTE mtr_c = 0; -static UINT mtr_r = 0; - - // ---- FDD -static void setfdcmode(REG8 drv, REG8 type, REG8 rpm) { +static BOOL setfdcmode(REG8 drv, REG8 type, REG8 rpm) { - if (drv < 4) { - fdc.chgreg = type; - fdc.rpm[drv] = rpm; - if (type & 2) { - CTRL_FDMEDIA = DISKTYPE_2HD; - } - else { - CTRL_FDMEDIA = DISKTYPE_2DD; - } + if (drv >= 4) { + return(FAILURE); + } + if ((rpm) && (!fdc.support144)) { + return(FAILURE); } + if ((fdc.chgreg ^ type) & 1) { + return(FAILURE); + } + fdc.chgreg = type; + fdc.rpm[drv] = rpm; + if (type & 2) { + CTRL_FDMEDIA = DISKTYPE_2HD; + } + else { + CTRL_FDMEDIA = DISKTYPE_2DD; + } + return(SUCCESS); } void fddbios_equip(REG8 type, BOOL clear) { @@ -47,11 +51,11 @@ void fddbios_equip(REG8 type, BOOL clear } if (type & 1) { diskequip &= 0xfff0; - diskequip |= 0x0003; + diskequip |= (fdc.equip & 0x0f); } else { - diskequip &= 0xf0ff; - diskequip |= 0x0300; + diskequip &= 0x0fff; + diskequip |= (fdc.equip & 0x0f) << 12; } SETBIOSMEM16(MEMW_DISK_EQUIP, diskequip); } @@ -67,12 +71,12 @@ static void biosfd_setchrn(void) { #if 0 static void biosfd_resultout(UINT32 result) { - BYTE *ptr; + UINT8 *ptr; ptr = mem + 0x00564 + (fdc.us*8); - ptr[0] = (BYTE)(result & 0xff) | (fdc.hd << 2) | fdc.us; - ptr[1] = (BYTE)(result >> 8); - ptr[2] = (BYTE)(result >> 16); + ptr[0] = (UINT8)(result & 0xff) | (fdc.hd << 2) | fdc.us; + ptr[1] = (UINT8)(result >> 8); + ptr[2] = (UINT8)(result >> 16); ptr[3] = fdc.C; ptr[4] = fdc.H; ptr[5] = fdc.R; @@ -92,7 +96,6 @@ static BOOL biosfd_seek(REG8 track, BOOL } } fdc.ncn = track; - mtr_c = track; if (fdd_seek()) { return(FAILURE); } @@ -121,7 +124,7 @@ static UINT16 fdfmt_biospara(REG8 type, off = 0x2361; // see bios.cpp } off += fdc.us * 2; - off = i286_memword_read(seg, off); + off = MEMR_READ16(seg, off); off += n * 8; if (!(CPU_AH & 0x40)) { off += 4; @@ -129,7 +132,7 @@ static UINT16 fdfmt_biospara(REG8 type, if (fmt) { off += 2; } - return(i286_memword_read(seg, off)); + return(MEMR_READ16(seg, off)); } @@ -147,7 +150,7 @@ enum { static void fdd_int(int result) { - if (result == FDCBIOS_NORESULT) { // ver0.29 + if (result == FDCBIOS_NORESULT) { return; } switch(CPU_AH & 0x0f) { @@ -160,6 +163,7 @@ static void fdd_int(int result) { case 0x0a: // READ ID case 0x0d: // フォーマット break; + default: return; } @@ -196,7 +200,17 @@ static void fdd_int(int result) { fdc.stat[fdc.us] |= FDCRLT_IC0 | FDCRLT_NW; fdcsend_error7(); break; + + default: + return; + } + if (fdc.chgreg & 1) { + mem[MEMB_DISK_INTL] &= ~(0x01 << fdc.us); + } + else { + mem[MEMB_DISK_INTH] &= ~(0x10 << fdc.us); } + CPU_IP = BIOSOFST_WAIT; } #if 1 @@ -224,12 +238,12 @@ static void b0patch(void) { REG8 c; REG8 cl; REG8 last; - addr = ES_BASE + CPU_BP; + addr = CPU_BP; size = CPU_BX; cnt = 0; last = 0; while(size--) { - c = i286_memoryread(addr++); + c = MEMR_READ8(CPU_ES, addr++); cl = 0; do { REG8 now = c & 0x80; @@ -253,13 +267,13 @@ static void b0patch(void) { } } if ((b0p.pos >> 3) < CPU_BX) { - UINT32 addr; + UINT addr; REG8 c; - addr = ES_BASE + CPU_BP + (b0p.pos >> 3); - c = i286_memoryread(addr); + addr = CPU_BP + (b0p.pos >> 3); + c = MEMR_READ8(CPU_ES, addr); c ^= (1 << (b0p.pos & 7)); b0p.pos++; - i286_memorywrite(addr, c); + MEMR_WRITE8(CPU_ES, addr, c); } } } @@ -277,21 +291,26 @@ static REG8 fdd_operate(REG8 type, REG8 UINT16 accesssize; UINT16 secsize; UINT16 para; - BYTE s; - BYTE ID[4]; - BYTE hd; + UINT8 s; + UINT8 ID[4]; + UINT8 hd; int result = FDCBIOS_NORESULT; UINT32 addr; + UINT8 mtr_c; + UINT mtr_r; + UINT fmode; - mtr_c = 0xff; + mtr_c = fdc.ncn; mtr_r = 0; // とりあえずBIOSの時は無視する - fdc.mf = 0xff; // ver0.29 + fdc.mf = 0xff; // TRACE_("int 1Bh", CPU_AH); - setfdcmode(CPU_AL & 3, type, rpm); + if (setfdcmode((REG8)(CPU_AL & 3), type, rpm) != SUCCESS) { + return(0x40); + } if ((CPU_AH & 0x0f) != 0x0a) { fdc.crcn = 0; @@ -318,23 +337,22 @@ static REG8 fdd_operate(REG8 type, REG8 } if (!fdd_diskready(fdc.us)) { fdd_int(FDCBIOS_NONREADY); - if (CPU_AH == 0x84) { // ver0.28 - return(0x68); // 新センスは 両用ドライブ情報も - } - if (CPU_AH == 0xc4) { // ver0.31 - if (np2cfg.usefd144) { - return(0x6c); + ret_ah = 0x60; + if ((CPU_AX & 0x8f40) == 0x8400) { + ret_ah |= 8; // 1MB/640KB両用ドライブ + if ((CPU_AH & 0x40) && (fdc.support144)) { + ret_ah |= 4; // 1.44対応ドライブ } - return(0x68); } - return(0x60); + return(ret_ah); } } - // 2DDのモード選択 // ver0.29 - if (type == DISKTYPE_2DD) { - if (!(mem[MEMB_F2DD_MODE] & (0x10 << fdc.us))) { - ndensity = 1; + // モード選択 // ver0.78 + fmode = (type & 1)?MEMB_F2HD_MODE:MEMB_F2DD_MODE; + if (!(CPU_AL & 0x80)) { + if (!(mem[fmode] & (0x10 << fdc.us))) { + ndensity = TRUE; } } @@ -386,7 +404,7 @@ static REG8 fdd_operate(REG8 type, REG8 break; } size -= accesssize; - mtr_r += accesssize; // ver0.26 + mtr_r += accesssize; if ((fdc.R++ == (UINT8)para) && (CPU_AH & 0x80) && (!fdc.hd)) { fdc.hd = 1; @@ -424,17 +442,16 @@ static REG8 fdd_operate(REG8 type, REG8 ret_ah |= 0x01; } else { // 2DD - if (mem[0x005ca] & (0x01 << fdc.us)) { - ret_ah++; + if (mem[fmode] & (0x01 << fdc.us)) { + ret_ah |= 0x01; } - if (mem[0x005ca] & (0x10 << fdc.us)) { // ver0.30 + if (mem[fmode] & (0x10 << fdc.us)) { ret_ah |= 0x04; } } - if (CPU_AH & 0x80) { // ver0.30 + if ((CPU_AX & 0x8f40) == 0x8400) { ret_ah |= 8; // 1MB/640KB両用ドライブ - if ((CPU_AH & 0x40) && - (np2cfg.usefd144)) { // ver0.31 + if ((CPU_AH & 0x40) && (fdc.support144)) { ret_ah |= 4; // 1.44対応ドライブ } } @@ -477,13 +494,13 @@ static REG8 fdd_operate(REG8 type, REG8 else { accesssize = size; } - i286_memx_read(addr, fdc.buf, accesssize); + MEML_READS(addr, fdc.buf, accesssize); if (fdd_write()) { break; } addr += accesssize; size -= accesssize; - mtr_r += accesssize; // ver0.26 + mtr_r += accesssize; if ((fdc.R++ == (UINT8)para) && (CPU_AH & 0x80) && (!fdc.hd)) { fdc.hd = 1; @@ -499,7 +516,7 @@ static REG8 fdd_operate(REG8 type, REG8 result = FDCBIOS_SUCCESS; } else { - ret_ah = fddlasterror; // 0xc0 // ver0.28 + ret_ah = fddlasterror; // 0xc0 result = FDCBIOS_WRITEERROR; } break; @@ -546,10 +563,10 @@ static REG8 fdd_operate(REG8 type, REG8 if (fdd_read()) { break; } - i286_memx_write(addr, fdc.buf, accesssize); + MEML_WRITES(addr, fdc.buf, accesssize); addr += accesssize; size -= accesssize; - mtr_r += accesssize; // ver0.26 + mtr_r += accesssize; if (fdc.R++ == (UINT8)para) { if ((CPU_AH & 0x80) && (!fdc.hd)) { fdc.hd = 1; @@ -587,7 +604,7 @@ static REG8 fdd_operate(REG8 type, REG8 } #endif else { - ret_ah = fddlasterror; // 0xc0; // ver0.28 + ret_ah = fddlasterror; // 0xc0; result = FDCBIOS_READERROR; } break; @@ -599,8 +616,8 @@ static REG8 fdd_operate(REG8 type, REG8 break; case 0x0a: // READ ID - fdc.mf = CPU_AH & 0x40; // ver0.29 - if (CPU_AH & 0x10) { // ver0.28 + fdc.mf = CPU_AH & 0x40; + if (CPU_AH & 0x10) { if (!biosfd_seek(CPU_CL, ndensity)) { result = FDCBIOS_SEEKSUCCESS; } @@ -611,10 +628,10 @@ static REG8 fdd_operate(REG8 type, REG8 } } if (fdd_readid()) { - ret_ah = fddlasterror; // 0xa0; // ver0.28 + ret_ah = fddlasterror; // 0xa0; break; } - if (fdc.N < 8) { // ver0.26 + if (fdc.N < 8) { mtr_r += 128 << fdc.N; } else { @@ -647,7 +664,7 @@ static REG8 fdd_operate(REG8 type, REG8 fdd_formatinit(); pos = CPU_BP; for (s=0; s> 4)]; + seg = mem[MEMX_DISK_XROM + (CPU_AL >> 4)]; if (seg) { - TRACEOUT(("call by %.4x:%.4x", - i286_memword_read(CPU_SS, CPU_SP+2), - i286_memword_read(CPU_SS, CPU_SP))); sp = CPU_SP; - i286_memword_write(CPU_SS, sp - 2, CPU_DS); - i286_memword_write(CPU_SS, sp - 4, CPU_SI); - i286_memword_write(CPU_SS, sp - 6, CPU_DI); - i286_memword_write(CPU_SS, sp - 8, CPU_ES); // +a - i286_memword_write(CPU_SS, sp - 10, CPU_BP); // +8 - i286_memword_write(CPU_SS, sp - 12, CPU_DX); // +6 - i286_memword_write(CPU_SS, sp - 14, CPU_CX); // +4 - i286_memword_write(CPU_SS, sp - 16, CPU_BX); // +2 - i286_memword_write(CPU_SS, sp - 18, CPU_AX); // +0 + MEMR_WRITE16(CPU_SS, sp - 2, CPU_DS); + MEMR_WRITE16(CPU_SS, sp - 4, CPU_SI); + MEMR_WRITE16(CPU_SS, sp - 6, CPU_DI); + MEMR_WRITE16(CPU_SS, sp - 8, CPU_ES); // +a + MEMR_WRITE16(CPU_SS, sp - 10, CPU_BP); // +8 + MEMR_WRITE16(CPU_SS, sp - 12, CPU_DX); // +6 + MEMR_WRITE16(CPU_SS, sp - 14, CPU_CX); // +4 + MEMR_WRITE16(CPU_SS, sp - 16, CPU_BX); // +2 + MEMR_WRITE16(CPU_SS, sp - 18, CPU_AX); // +0 +#if 0 + TRACEOUT(("call by %.4x:%.4x", + MEMR_READ16(CPU_SS, CPU_SP+2), + MEMR_READ16(CPU_SS, CPU_SP))); TRACEOUT(("bypass to %.4x:0018", seg << 8)); TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x", CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, CPU_ES, CPU_BP)); +#endif sp -= 18; CPU_SP = sp; CPU_BP = sp; @@ -887,30 +912,40 @@ void bios0x1b(void) { CPU_IP = 0x18; return; } -} +#endif + +#if defined(SUPPORT_SCSI) + if ((CPU_AL & 0xf0) == 0xc0) { + TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x", + MEMR_READ16(CPU_SS, CPU_SP+2), + MEMR_READ16(CPU_SS, CPU_SP), + CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP)); + scsicmd_bios(); + return; + } #endif switch(CPU_AL & 0xf0) { case 0x90: - ret_ah = fdd_operate(3, 0, 0); + ret_ah = fdd_operate(3, 0, FALSE); break; case 0x30: case 0xb0: - ret_ah = fdd_operate(3, 1, 0); + ret_ah = fdd_operate(3, 1, FALSE); break; case 0x10: - ret_ah = fdd_operate(1, 0, 0); + ret_ah = fdd_operate(1, 0, FALSE); break; case 0x70: case 0xf0: - ret_ah = fdd_operate(0, 0, 0); + ret_ah = fdd_operate(0, 0, FALSE); break; case 0x50: - ret_ah = fdd_operate(0, 0, 1); + ret_ah = fdd_operate(0, 0, TRUE); break; case 0x00: @@ -932,16 +967,46 @@ void bios0x1b(void) { #if 0 TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \ "ES=%04x BP=%04x \nret=%02x", - i286_memword_read(CPU_SS, CPU_SP+2), - i286_memword_read(CPU_SS, CPU_SP), + MEMR_READ16(CPU_SS, CPU_SP+2), + MEMR_READ16(CPU_SS, CPU_SP), CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, CPU_ES, CPU_BP, ret_ah)); #endif CPU_AH = ret_ah; - flag = i286_membyte_read(CPU_SS, CPU_SP+4) & 0xfe; + flag = MEMR_READ8(CPU_SS, CPU_SP+4) & 0xfe; if (ret_ah >= 0x20) { flag += 1; } - i286_membyte_write(CPU_SS, CPU_SP + 4, flag); + MEMR_WRITE8(CPU_SS, CPU_SP + 4, flag); +} + +UINT bios0x1b_wait(void) { + + UINT addr; + REG8 bit; + + if (fddmtr.busy) { + CPU_REMCLOCK = -1; + } + else { + if (fdc.chgreg & 1) { + addr = MEMB_DISK_INTL; + bit = 0x01; + } + else { + addr = MEMB_DISK_INTH; + bit = 0x10; + } + bit <<= fdc.us; + if (mem[addr] & bit) { + mem[addr] &= ~bit; + return(0); + } + else { + CPU_REMCLOCK -= 1000; + } + } + CPU_IP--; + return(1); }