--- np2/bios/bios1b.c	2004/03/06 18:25:35	1.23
+++ np2/bios/bios1b.c	2005/05/13 05:46:24	1.33
@@ -68,12 +68,12 @@ static void biosfd_setchrn(void) {
 #if 0
 static void biosfd_resultout(UINT32 result) {
 
-	BYTE	*ptr;
+	UINT8	*ptr;
 
 	ptr = mem + 0x00564 + (fdc.us*8);
-	ptr[0] = (BYTE)(result & 0xff) | (fdc.hd << 2) | fdc.us;
-	ptr[1] = (BYTE)(result >> 8);
-	ptr[2] = (BYTE)(result >> 16);
+	ptr[0] = (UINT8)(result & 0xff) | (fdc.hd << 2) | fdc.us;
+	ptr[1] = (UINT8)(result >> 8);
+	ptr[2] = (UINT8)(result >> 16);
 	ptr[3] = fdc.C;
 	ptr[4] = fdc.H;
 	ptr[5] = fdc.R;
@@ -121,7 +121,7 @@ static UINT16 fdfmt_biospara(REG8 type, 
 		off = 0x2361;									// see bios.cpp
 	}
 	off += fdc.us * 2;
-	off = i286_memword_read(seg, off);
+	off = MEML_READ16(seg, off);
 	off += n * 8;
 	if (!(CPU_AH & 0x40)) {
 		off += 4;
@@ -129,7 +129,7 @@ static UINT16 fdfmt_biospara(REG8 type, 
 	if (fmt) {
 		off += 2;
 	}
-	return(i286_memword_read(seg, off));
+	return(MEML_READ16(seg, off));
 }
 
 
@@ -147,7 +147,7 @@ enum {
 
 static void fdd_int(int result) {
 
-	if (result == FDCBIOS_NORESULT) {						// ver0.29
+	if (result == FDCBIOS_NORESULT) {
 		return;
 	}
 	switch(CPU_AH & 0x0f) {
@@ -202,10 +202,10 @@ static void fdd_int(int result) {
 			return;
 	}
 	if (fdc.chgreg & 1) {
-		mem[0x0055e] &= ~(0x01 << fdc.us);
+		mem[MEMB_DISK_INTL] &= ~(0x01 << fdc.us);
 	}
 	else {
-		mem[0x0055f] &= ~(0x10 << fdc.us);
+		mem[MEMB_DISK_INTH] &= ~(0x10 << fdc.us);
 	}
 	CPU_IP = BIOSOFST_WAIT;
 }
@@ -288,19 +288,20 @@ static REG8 fdd_operate(REG8 type, REG8 
 	UINT16	accesssize;
 	UINT16	secsize;
 	UINT16	para;
-	BYTE	s;
-	BYTE	ID[4];
-	BYTE	hd;
+	UINT8	s;
+	UINT8	ID[4];
+	UINT8	hd;
 	int		result = FDCBIOS_NORESULT;
 	UINT32	addr;
 	UINT8	mtr_c;
 	UINT	mtr_r;
+	UINT	fmode;
 
 	mtr_c = fdc.ncn;
 	mtr_r = 0;
 
 	// とりあえずBIOSの時は無視する
-	fdc.mf = 0xff;						// ver0.29
+	fdc.mf = 0xff;
 
 //	TRACE_("int 1Bh", CPU_AH);
 
@@ -333,23 +334,22 @@ static REG8 fdd_operate(REG8 type, REG8 
 		}
 		if (!fdd_diskready(fdc.us)) {
 			fdd_int(FDCBIOS_NONREADY);
-			if (CPU_AH == 0x84) {								// ver0.28
-				return(0x68);			// 新センスは 両用ドライブ情報も
-			}
-			if (CPU_AH == 0xc4) {								// ver0.31
-				if (fdc.support144) {
-					return(0x6c);
+			ret_ah = 0x60;
+			if ((CPU_AX & 0x8f40) == 0x8400) {
+				ret_ah |= 8;					// 1MB/640KB両用ドライブ
+				if ((CPU_AH & 0x40) && (fdc.support144)) {
+					ret_ah |= 4;				// 1.44対応ドライブ
 				}
-				return(0x68);
 			}
-			return(0x60);
+			return(ret_ah);
 		}
 	}
 
-	// 2DDのモード選択							// ver0.29
-	if (type == DISKTYPE_2DD) {
-		if (!(mem[MEMB_F2DD_MODE] & (0x10 << fdc.us))) {
-			ndensity = 1;
+	// モード選択													// ver0.78
+	fmode = (type & 1)?MEMB_F2HD_MODE:MEMB_F2DD_MODE;
+	if (!(CPU_AL & 0x80)) {
+		if (!(mem[fmode] & (0x10 << fdc.us))) {
+			ndensity = TRUE;
 		}
 	}
 
@@ -401,7 +401,7 @@ static REG8 fdd_operate(REG8 type, REG8 
 					break;
 				}
 				size -= accesssize;
-				mtr_r += accesssize;						// ver0.26
+				mtr_r += accesssize;
 				if ((fdc.R++ == (UINT8)para) &&
 					(CPU_AH & 0x80) && (!fdc.hd)) {
 					fdc.hd = 1;
@@ -439,14 +439,14 @@ static REG8 fdd_operate(REG8 type, REG8 
 				ret_ah |= 0x01;
 			}
 			else {								// 2DD
-				if (mem[0x005ca] & (0x01 << fdc.us)) {
-					ret_ah++;
+				if (mem[fmode] & (0x01 << fdc.us)) {
+					ret_ah |= 0x01;
 				}
-				if (mem[0x005ca] & (0x10 << fdc.us)) {				// ver0.30
+				if (mem[fmode] & (0x10 << fdc.us)) {
 					ret_ah |= 0x04;
 				}
 			}
-			if (CPU_AH & 0x80) {				// ver0.30
+			if ((CPU_AX & 0x8f40) == 0x8400) {
 				ret_ah |= 8;					// 1MB/640KB両用ドライブ
 				if ((CPU_AH & 0x40) && (fdc.support144)) {
 					ret_ah |= 4;				// 1.44対応ドライブ
@@ -497,7 +497,7 @@ static REG8 fdd_operate(REG8 type, REG8 
 				}
 				addr += accesssize;
 				size -= accesssize;
-				mtr_r += accesssize;						// ver0.26
+				mtr_r += accesssize;
 				if ((fdc.R++ == (UINT8)para) &&
 					(CPU_AH & 0x80) && (!fdc.hd)) {
 					fdc.hd = 1;
@@ -513,7 +513,7 @@ static REG8 fdd_operate(REG8 type, REG8 
 				result = FDCBIOS_SUCCESS;
 			}
 			else {
-				ret_ah = fddlasterror;			// 0xc0		// ver0.28
+				ret_ah = fddlasterror;			// 0xc0
 				result = FDCBIOS_WRITEERROR;
 			}
 			break;
@@ -563,7 +563,7 @@ static REG8 fdd_operate(REG8 type, REG8 
 				MEML_WRITE(addr, fdc.buf, accesssize);
 				addr += accesssize;
 				size -= accesssize;
-				mtr_r += accesssize;						// ver0.26
+				mtr_r += accesssize;
 				if (fdc.R++ == (UINT8)para) {
 					if ((CPU_AH & 0x80) && (!fdc.hd)) {
 						fdc.hd = 1;
@@ -601,7 +601,7 @@ static REG8 fdd_operate(REG8 type, REG8 
 			}
 #endif
 			else {
-				ret_ah = fddlasterror;				// 0xc0;	// ver0.28
+				ret_ah = fddlasterror;				// 0xc0;
 				result = FDCBIOS_READERROR;
 			}
 			break;
@@ -613,8 +613,8 @@ static REG8 fdd_operate(REG8 type, REG8 
 			break;
 
 		case 0x0a:						// READ ID
-			fdc.mf = CPU_AH & 0x40;							// ver0.29
-			if (CPU_AH & 0x10) {							// ver0.28
+			fdc.mf = CPU_AH & 0x40;
+			if (CPU_AH & 0x10) {
 				if (!biosfd_seek(CPU_CL, ndensity)) {
 					result = FDCBIOS_SEEKSUCCESS;
 				}
@@ -625,10 +625,10 @@ static REG8 fdd_operate(REG8 type, REG8 
 				}
 			}
 			if (fdd_readid()) {
-				ret_ah = fddlasterror;			// 0xa0;	// ver0.28
+				ret_ah = fddlasterror;			// 0xa0;
 				break;
 			}
-			if (fdc.N < 8) {								// ver0.26
+			if (fdc.N < 8) {
 				mtr_r += 128 << fdc.N;
 			}
 			else {
@@ -673,6 +673,18 @@ static REG8 fdd_operate(REG8 type, REG8 
 			}
 			ret_ah = 0x00;
 			break;
+
+		case 0x0e:													// ver0.78
+			if (CPU_AH & 0x80) {			// 密度設定
+				mem[fmode] &= 0x0f;
+				mem[fmode] |= (UINT8)((CPU_AH & 0x0f) << 4);
+			}
+			else {							// 面設定
+				mem[fmode] &= 0xf0;
+				mem[fmode] |= (UINT8)(CPU_AH & 0x0f);
+			}
+			ret_ah = 0x00;
+			break;
 	}
 	fdd_int(result);
 	if (mtr_c != fdc.ncn) {
@@ -737,7 +749,7 @@ static UINT16 boot_fd1(REG8 type, REG8 r
 	return(bootseg);
 }
 
-static UINT16 boot_fd(REG8 drv, REG8 type) {						// ver0.27
+static UINT16 boot_fd(REG8 drv, REG8 type) {
 
 	UINT16	bootseg;
 
@@ -766,11 +778,11 @@ static UINT16 boot_fd(REG8 drv, REG8 typ
 			return(bootseg);
 		}
 	}
-	if (type & 2) {										// ver0.29
+	if (type & 2) {
 		// 2DD
 		bootseg = boot_fd1(0, 0);
 		if (bootseg) {
-			mem[MEMB_DISK_BOOT] = (BYTE)(0x70 + drv);
+			mem[MEMB_DISK_BOOT] = (UINT8)(0x70 + drv);
 			fddbios_equip(0, TRUE);
 			return(bootseg);
 		}
@@ -792,7 +804,7 @@ static REG16 boot_hd(REG8 drv) {
 
 REG16 bootstrapload(void) {
 
-	BYTE	i;
+	UINT8	i;
 	REG16	bootseg;
 
 //	fdmode = 0;
@@ -859,38 +871,26 @@ void bios0x1b(void) {
 	REG8	ret_ah;
 	REG8	flag;
 
-#if defined(SUPPORT_SCSI)
-	if ((CPU_AL & 0xf0) == 0xc0) {
-		TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x",
-							i286_memword_read(CPU_SS, CPU_SP+2),
-							i286_memword_read(CPU_SS, CPU_SP),
-							CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP));
-		scsicmd_bios();
-		return;
-	}
-#endif
-
 #if 1			// bypass to disk bios
-{
 	REG8	seg;
 	UINT	sp;
 
-	seg = mem[0x004b0 + (CPU_AL >> 4)];
+	seg = mem[MEMX_DISK_XROM + (CPU_AL >> 4)];
 	if (seg) {
-		TRACEOUT(("call by %.4x:%.4x",
-							i286_memword_read(CPU_SS, CPU_SP+2),
-							i286_memword_read(CPU_SS, CPU_SP)));
 		sp = CPU_SP;
-		i286_memword_write(CPU_SS, sp - 2, CPU_DS);
-		i286_memword_write(CPU_SS, sp - 4, CPU_SI);
-		i286_memword_write(CPU_SS, sp - 6, CPU_DI);
-		i286_memword_write(CPU_SS, sp - 8, CPU_ES);			// +a
-		i286_memword_write(CPU_SS, sp - 10, CPU_BP);		// +8
-		i286_memword_write(CPU_SS, sp - 12, CPU_DX);		// +6
-		i286_memword_write(CPU_SS, sp - 14, CPU_CX);		// +4
-		i286_memword_write(CPU_SS, sp - 16, CPU_BX);		// +2
-		i286_memword_write(CPU_SS, sp - 18, CPU_AX);		// +0
+		MEML_WRITE16(CPU_SS, sp - 2, CPU_DS);
+		MEML_WRITE16(CPU_SS, sp - 4, CPU_SI);
+		MEML_WRITE16(CPU_SS, sp - 6, CPU_DI);
+		MEML_WRITE16(CPU_SS, sp - 8, CPU_ES);		// +a
+		MEML_WRITE16(CPU_SS, sp - 10, CPU_BP);		// +8
+		MEML_WRITE16(CPU_SS, sp - 12, CPU_DX);		// +6
+		MEML_WRITE16(CPU_SS, sp - 14, CPU_CX);		// +4
+		MEML_WRITE16(CPU_SS, sp - 16, CPU_BX);		// +2
+		MEML_WRITE16(CPU_SS, sp - 18, CPU_AX);		// +0
 #if 0
+		TRACEOUT(("call by %.4x:%.4x",
+							MEML_READ16(CPU_SS, CPU_SP+2),
+							MEML_READ16(CPU_SS, CPU_SP)));
 		TRACEOUT(("bypass to %.4x:0018", seg << 8));
 		TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x",
 							CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,
@@ -906,30 +906,40 @@ void bios0x1b(void) {
 		CPU_IP = 0x18;
 		return;
 	}
-}
+#endif
+
+#if defined(SUPPORT_SCSI)
+	if ((CPU_AL & 0xf0) == 0xc0) {
+		TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x",
+							MEML_READ16(CPU_SS, CPU_SP+2),
+							MEML_READ16(CPU_SS, CPU_SP),
+							CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP));
+		scsicmd_bios();
+		return;
+	}
 #endif
 
 	switch(CPU_AL & 0xf0) {
 		case 0x90:
-			ret_ah = fdd_operate(3, 0, 0);
+			ret_ah = fdd_operate(3, 0, FALSE);
 			break;
 
 		case 0x30:
 		case 0xb0:
-			ret_ah = fdd_operate(3, 1, 0);
+			ret_ah = fdd_operate(3, 1, FALSE);
 			break;
 
 		case 0x10:
-			ret_ah = fdd_operate(1, 0, 0);
+			ret_ah = fdd_operate(1, 0, FALSE);
 			break;
 
 		case 0x70:
 		case 0xf0:
-			ret_ah = fdd_operate(0, 0, 0);
+			ret_ah = fdd_operate(0, 0, FALSE);
 			break;
 
 		case 0x50:
-			ret_ah = fdd_operate(0, 0, 1);
+			ret_ah = fdd_operate(0, 0, TRUE);
 			break;
 
 		case 0x00:
@@ -948,19 +958,50 @@ void bios0x1b(void) {
 			ret_ah = 0x40;
 			break;
 	}
-#if 1
+#if 0
 	TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n"	\
 						"ES=%04x BP=%04x \nret=%02x",
-							i286_memword_read(CPU_SS, CPU_SP+2),
-							i286_memword_read(CPU_SS, CPU_SP),
+							MEML_READ16(CPU_SS, CPU_SP+2),
+							MEML_READ16(CPU_SS, CPU_SP),
 							CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH,
 							CPU_ES, CPU_BP, ret_ah));
 #endif
 	CPU_AH = ret_ah;
-	flag = i286_membyte_read(CPU_SS, CPU_SP+4) & 0xfe;
+	flag = MEML_READ8(CPU_SS, CPU_SP+4) & 0xfe;
 	if (ret_ah >= 0x20) {
 		flag += 1;
 	}
-	i286_membyte_write(CPU_SS, CPU_SP + 4, flag);
+	MEML_WRITE8(CPU_SS, CPU_SP + 4, flag);
+}
+
+UINT bios0x1b_wait(void) {
+
+	UINT	addr;
+	REG8	bit;
+
+	if (fddmtr.busy) {
+		CPU_IP--;
+		CPU_REMCLOCK = -1;
+	}
+	else {
+		if (fdc.chgreg & 1) {
+			addr = MEMB_DISK_INTL;
+			bit = 0x01;
+		}
+		else {
+			addr = MEMB_DISK_INTH;
+			bit = 0x10;
+		}
+		bit <<= fdc.us;
+		if (mem[addr] & bit) {
+			mem[addr] &= ~bit;
+			return(0);
+		}
+		else {
+			CPU_REMCLOCK -= 1000;
+		}
+	}
+	CPU_IP--;
+	return(1);
 }