--- np2/bios/bios1b.c 2005/02/27 15:07:36 1.32 +++ np2/bios/bios1b.c 2005/05/20 13:59:46 1.36 @@ -27,6 +27,9 @@ static BOOL setfdcmode(REG8 drv, REG8 ty if ((rpm) && (!fdc.support144)) { return(FAILURE); } + if ((fdc.chgreg ^ type) & 1) { + return(FAILURE); + } fdc.chgreg = type; fdc.rpm[drv] = rpm; if (type & 2) { @@ -121,7 +124,7 @@ static UINT16 fdfmt_biospara(REG8 type, off = 0x2361; // see bios.cpp } off += fdc.us * 2; - off = MEML_READ16(seg, off); + off = MEMR_READ16(seg, off); off += n * 8; if (!(CPU_AH & 0x40)) { off += 4; @@ -129,7 +132,7 @@ static UINT16 fdfmt_biospara(REG8 type, if (fmt) { off += 2; } - return(MEML_READ16(seg, off)); + return(MEMR_READ16(seg, off)); } @@ -235,12 +238,12 @@ static void b0patch(void) { REG8 c; REG8 cl; REG8 last; - addr = ES_BASE + CPU_BP; + addr = CPU_BP; size = CPU_BX; cnt = 0; last = 0; while(size--) { - c = i286_memoryread(addr++); + c = MEMR_READ8(ES_BASE, addr++); cl = 0; do { REG8 now = c & 0x80; @@ -264,13 +267,13 @@ static void b0patch(void) { } } if ((b0p.pos >> 3) < CPU_BX) { - UINT32 addr; + UINT addr; REG8 c; - addr = ES_BASE + CPU_BP + (b0p.pos >> 3); - c = i286_memoryread(addr); + addr = CPU_BP + (b0p.pos >> 3); + c = MEMR_READ8(CPU_ES, addr); c ^= (1 << (b0p.pos & 7)); b0p.pos++; - i286_memorywrite(addr, c); + MEMR_WRITE8(CPU_ES, addr, c); } } } @@ -334,16 +337,14 @@ static REG8 fdd_operate(REG8 type, REG8 } if (!fdd_diskready(fdc.us)) { fdd_int(FDCBIOS_NONREADY); - if (CPU_AH == 0x84) { - return(0x68); // 新センスは 両用ドライブ情報も - } - if (CPU_AH == 0xc4) { // ver0.31 - if (fdc.support144) { - return(0x6c); + ret_ah = 0x60; + if ((CPU_AX & 0x8f40) == 0x8400) { + ret_ah |= 8; // 1MB/640KB両用ドライブ + if ((CPU_AH & 0x40) && (fdc.support144)) { + ret_ah |= 4; // 1.44対応ドライブ } - return(0x68); } - return(0x60); + return(ret_ah); } } @@ -444,11 +445,11 @@ static REG8 fdd_operate(REG8 type, REG8 if (mem[fmode] & (0x01 << fdc.us)) { ret_ah |= 0x01; } - if (mem[fmode] & (0x10 << fdc.us)) { // ver0.30 + if (mem[fmode] & (0x10 << fdc.us)) { ret_ah |= 0x04; } } - if (CPU_AH & 0x80) { // ver0.30 + if ((CPU_AX & 0x8f40) == 0x8400) { ret_ah |= 8; // 1MB/640KB両用ドライブ if ((CPU_AH & 0x40) && (fdc.support144)) { ret_ah |= 4; // 1.44対応ドライブ @@ -493,7 +494,7 @@ static REG8 fdd_operate(REG8 type, REG8 else { accesssize = size; } - MEML_READ(addr, fdc.buf, accesssize); + MEML_READS(addr, fdc.buf, accesssize); if (fdd_write()) { break; } @@ -562,7 +563,7 @@ static REG8 fdd_operate(REG8 type, REG8 if (fdd_read()) { break; } - MEML_WRITE(addr, fdc.buf, accesssize); + MEML_WRITES(addr, fdc.buf, accesssize); addr += accesssize; size -= accesssize; mtr_r += accesssize; @@ -663,7 +664,7 @@ static REG8 fdd_operate(REG8 type, REG8 fdd_formatinit(); pos = CPU_BP; for (s=0; s> 4)]; if (seg) { sp = CPU_SP; - MEML_WRITE16(CPU_SS, sp - 2, CPU_DS); - MEML_WRITE16(CPU_SS, sp - 4, CPU_SI); - MEML_WRITE16(CPU_SS, sp - 6, CPU_DI); - MEML_WRITE16(CPU_SS, sp - 8, CPU_ES); // +a - MEML_WRITE16(CPU_SS, sp - 10, CPU_BP); // +8 - MEML_WRITE16(CPU_SS, sp - 12, CPU_DX); // +6 - MEML_WRITE16(CPU_SS, sp - 14, CPU_CX); // +4 - MEML_WRITE16(CPU_SS, sp - 16, CPU_BX); // +2 - MEML_WRITE16(CPU_SS, sp - 18, CPU_AX); // +0 + MEMR_WRITE16(CPU_SS, sp - 2, CPU_DS); + MEMR_WRITE16(CPU_SS, sp - 4, CPU_SI); + MEMR_WRITE16(CPU_SS, sp - 6, CPU_DI); + MEMR_WRITE16(CPU_SS, sp - 8, CPU_ES); // +a + MEMR_WRITE16(CPU_SS, sp - 10, CPU_BP); // +8 + MEMR_WRITE16(CPU_SS, sp - 12, CPU_DX); // +6 + MEMR_WRITE16(CPU_SS, sp - 14, CPU_CX); // +4 + MEMR_WRITE16(CPU_SS, sp - 16, CPU_BX); // +2 + MEMR_WRITE16(CPU_SS, sp - 18, CPU_AX); // +0 #if 0 TRACEOUT(("call by %.4x:%.4x", - MEML_READ16(CPU_SS, CPU_SP+2), - MEML_READ16(CPU_SS, CPU_SP))); + MEMR_READ16(CPU_SS, CPU_SP+2), + MEMR_READ16(CPU_SS, CPU_SP))); TRACEOUT(("bypass to %.4x:0018", seg << 8)); TRACEOUT(("AX=%04x BX=%04x %02x:%02x:%02x:%02x ES=%04x BP=%04x", CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, @@ -913,8 +917,8 @@ void bios0x1b(void) { #if defined(SUPPORT_SCSI) if ((CPU_AL & 0xf0) == 0xc0) { TRACEOUT(("%.4x:%.4x AX=%.4x BX=%.4x CX=%.4x DX=%.4 ES=%.4x BP=%.4x", - MEML_READ16(CPU_SS, CPU_SP+2), - MEML_READ16(CPU_SS, CPU_SP), + MEMR_READ16(CPU_SS, CPU_SP+2), + MEMR_READ16(CPU_SS, CPU_SP), CPU_AX, CPU_BX, CPU_CX, CPU_DX, CPU_ES, CPU_BP)); scsicmd_bios(); return; @@ -963,17 +967,17 @@ void bios0x1b(void) { #if 0 TRACEOUT(("%04x:%04x AX=%04x BX=%04x %02x:%02x:%02x:%02x\n" \ "ES=%04x BP=%04x \nret=%02x", - MEML_READ16(CPU_SS, CPU_SP+2), - MEML_READ16(CPU_SS, CPU_SP), + MEMR_READ16(CPU_SS, CPU_SP+2), + MEMR_READ16(CPU_SS, CPU_SP), CPU_AX, CPU_BX, CPU_CL, CPU_DH, CPU_DL, CPU_CH, CPU_ES, CPU_BP, ret_ah)); #endif CPU_AH = ret_ah; - flag = MEML_READ8(CPU_SS, CPU_SP+4) & 0xfe; + flag = MEMR_READ8(CPU_SS, CPU_SP+4) & 0xfe; if (ret_ah >= 0x20) { flag += 1; } - MEML_WRITE8(CPU_SS, CPU_SP + 4, flag); + MEMR_WRITE8(CPU_SS, CPU_SP + 4, flag); } UINT bios0x1b_wait(void) { @@ -982,7 +986,6 @@ UINT bios0x1b_wait(void) { REG8 bit; if (fddmtr.busy) { - CPU_IP--; CPU_REMCLOCK = -1; } else {