--- np2/bios/bios1c.c	2004/01/13 05:30:58	1.5
+++ np2/bios/bios1c.c	2005/05/20 13:59:46	1.11
@@ -9,31 +9,19 @@
 #include	"biosmem.h"
 
 
-void bios0x1c_03(void) {
-
-	iocore_out8(0x71, 0x00);
-	if (pccore.cpumode & CPUMODE_8MHz) {
-		iocore_out8(0x71, 0x4e);				// 4MHz
-	}
-	else {
-		iocore_out8(0x71, 0x60);				// 5MHz
-	}
-	pic.pi[0].imr &= ~(PIC_SYSTEMTIMER);
-}
-
 void bios0x1c(void) {
 
-	BYTE	buf[6];
+	UINT8	buf[6];
 
 	switch(CPU_AH) {
 		case 0x00:					// get system timer
 			calendar_get(buf);
-			i286_memstr_write(CPU_ES, CPU_BX, buf, 6);
+			MEMR_WRITES(CPU_ES, CPU_BX, buf, 6);
 			break;
 
 		case 0x01:					// put system timer
-			i286_memstr_read(CPU_ES, CPU_BX, buf, 6);
-			mem[MEMB_MSW8] = buf[0];								// ver0.29
+			MEMR_READS(CPU_ES, CPU_BX, buf, 6);
+			mem[MEMB_MSW8] = buf[0];
 			calendar_set(buf);
 			break;
 
@@ -42,11 +30,17 @@ void bios0x1c(void) {
 			SETBIOSMEM16(0x0001e, CPU_ES);
 			SETBIOSMEM16(0x0058a, CPU_CX);
 			iocore_out8(0x77, 0x36);
-			bios0x1c_03();
-			break;
+			/* through */
 
 		case 0x03:					// continue interval timer
-			bios0x1c_03();
+			iocore_out8(0x71, 0x00);
+			if (pccore.cpumode & CPUMODE_8MHZ) {
+				iocore_out8(0x71, 0x4e);				// 4MHz
+			}
+			else {
+				iocore_out8(0x71, 0x60);				// 5MHz
+			}
+			pic.pi[0].imr &= ~(PIC_SYSTEMTIMER);
 			break;
 	}
 }