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| version 1.8, 2004/01/28 23:36:13 | version 1.16, 2005/02/07 14:46:07 |
|---|---|
| Line 47 static REG8 sxsi_pos(UINT type, SXSIDEV | Line 47 static REG8 sxsi_pos(UINT type, SXSIDEV |
| static REG8 sxsibios_write(UINT type, SXSIDEV sxsi) { | static REG8 sxsibios_write(UINT type, SXSIDEV sxsi) { |
| REG8 ret; | REG8 ret; |
| UINT32 addr; | |
| UINT size; | UINT size; |
| long pos; | long pos; |
| UINT32 addr; | |
| UINT r; | UINT r; |
| BYTE work[1024]; | UINT8 work[1024]; |
| addr = (CPU_ES << 4) + CPU_BP; | |
| size = CPU_BX; | size = CPU_BX; |
| if (!size) { | if (!size) { |
| size = 0x10000; | size = 0x10000; |
| } | } |
| ret = sxsi_pos(type, sxsi, &pos); | ret = sxsi_pos(type, sxsi, &pos); |
| if (!ret) { | if (!ret) { |
| addr = (CPU_ES << 4) + CPU_BP; | |
| while(size) { | while(size) { |
| r = min(size, sxsi->size); | r = min(size, sxsi->size); |
| i286_memx_read(addr, work, r); | MEML_READ(addr, work, r); |
| ret = sxsi_write(CPU_AL, pos, work, r); | ret = sxsi_write(CPU_AL, pos, work, r); |
| if (ret >= 0x20) { | if (ret >= 0x20) { |
| break; | break; |
| } | } |
| size -= r; | |
| addr += r; | addr += r; |
| size -= r; | |
| pos++; | pos++; |
| } | } |
| } | } |
| Line 78 static REG8 sxsibios_write(UINT type, SX | Line 78 static REG8 sxsibios_write(UINT type, SX |
| static REG8 sxsibios_read(UINT type, SXSIDEV sxsi) { | static REG8 sxsibios_read(UINT type, SXSIDEV sxsi) { |
| REG8 ret; | REG8 ret; |
| UINT32 addr; | |
| UINT size; | UINT size; |
| long pos; | long pos; |
| UINT32 addr; | |
| UINT r; | UINT r; |
| BYTE work[1024]; | UINT8 work[1024]; |
| addr = (CPU_ES << 4) + CPU_BP; | |
| size = CPU_BX; | size = CPU_BX; |
| if (!size) { | if (!size) { |
| size = 0x10000; | size = 0x10000; |
| } | } |
| ret = sxsi_pos(type, sxsi, &pos); | ret = sxsi_pos(type, sxsi, &pos); |
| if (!ret) { | if (!ret) { |
| addr = (CPU_ES << 4) + CPU_BP; | |
| while(size) { | while(size) { |
| r = min(size, sxsi->size); | r = min(size, sxsi->size); |
| ret = sxsi_read(CPU_AL, pos, work, r); | ret = sxsi_read(CPU_AL, pos, work, r); |
| if (ret >= 0x20) { | if (ret >= 0x20) { |
| break; | break; |
| } | } |
| i286_memx_write(addr, work, r); | MEML_WRITE(addr, work, r); |
| size -= r; | |
| addr += r; | addr += r; |
| size -= r; | |
| pos++; | pos++; |
| } | } |
| } | } |
| Line 186 static REG8 sasibios_init(UINT type, SXS | Line 186 static REG8 sasibios_init(UINT type, SXS |
| static REG8 sasibios_sense(UINT type, SXSIDEV sxsi) { | static REG8 sasibios_sense(UINT type, SXSIDEV sxsi) { |
| TRACEOUT(("sasibios_sense type=%d", type)); | |
| if (type == SXSIBIOS_SASI) { | if (type == SXSIBIOS_SASI) { |
| return((REG8)((sxsi->type >> 8) & 7)); | return((REG8)((sxsi->type >> 8) & 7)); |
| } | } |
| Line 250 REG8 sasibios_operate(void) { | Line 249 REG8 sasibios_operate(void) { |
| static void scsibios_set(REG8 drv, REG8 sectors, REG8 surfaces, | static void scsibios_set(REG8 drv, REG8 sectors, REG8 surfaces, |
| REG16 cylinders, REG16 size, BOOL hwsec) { | REG16 cylinders, REG16 size, BOOL hwsec) { |
| BYTE *scsiinf; | UINT8 *scsiinf; |
| UINT16 inf; | UINT16 inf; |
| scsiinf = mem + 0x00460 + ((drv & 7) * 4); | scsiinf = mem + 0x00460 + ((drv & 7) * 4); |
| Line 296 static REG8 scsibios_init(UINT type, SXS | Line 295 static REG8 scsibios_init(UINT type, SXS |
| static REG8 scsibios_sense(UINT type, SXSIDEV sxsi) { | static REG8 scsibios_sense(UINT type, SXSIDEV sxsi) { |
| BYTE *scsiinf; | UINT8 *scsiinf; |
| scsiinf = mem + 0x00460 + ((CPU_AL & 7) * 4); | scsiinf = mem + 0x00460 + ((CPU_AL & 7) * 4); |
| if (CPU_AH == 0x24) { | if (CPU_AH == 0x24) { |
| Line 315 static REG8 scsibios_sense(UINT type, SX | Line 314 static REG8 scsibios_sense(UINT type, SX |
| CPU_BX = 256 << ((scsiinf[3] >> 4) & 3); | CPU_BX = 256 << ((scsiinf[3] >> 4) & 3); |
| } | } |
| (void)type; | (void)type; |
| (void)sxsi; | |
| return(0x00); | return(0x00); |
| } | } |
| Line 374 REG8 scsibios_operate(void) { | Line 374 REG8 scsibios_operate(void) { |
| // ---- np2sysp | // ---- np2sysp |
| #if defined(SUPPORT_SASI) || defined(SUPPORT_SCSI) | #if defined(SUPPORT_IDEIO) || defined(SUPPORT_SASI) || defined(SUPPORT_SCSI) |
| typedef struct { | typedef struct { |
| UINT16 ax; | UINT16 ax; |
| UINT16 cx; | UINT16 cx; |
| Line 417 static void reg_pop(const REGBAK *r) { | Line 417 static void reg_pop(const REGBAK *r) { |
| } | } |
| typedef struct { | typedef struct { |
| BYTE r_ax[2]; | UINT8 r_ax[2]; |
| BYTE r_bx[2]; | UINT8 r_bx[2]; |
| BYTE r_cx[2]; | UINT8 r_cx[2]; |
| BYTE r_dx[2]; | UINT8 r_dx[2]; |
| BYTE r_bp[2]; | UINT8 r_bp[2]; |
| BYTE r_es[2]; | UINT8 r_es[2]; |
| BYTE r_di[2]; | UINT8 r_di[2]; |
| BYTE r_si[2]; | UINT8 r_si[2]; |
| BYTE r_ds[2]; | UINT8 r_ds[2]; |
| } B1BREG; | } B1BREG; |
| static void reg_load(UINT seg, UINT off) { | static void reg_load(UINT seg, UINT off) { |
| B1BREG r; | B1BREG r; |
| i286_memstr_read(seg, off, &r, sizeof(r)); | MEML_READSTR(seg, off, &r, sizeof(r)); |
| CPU_FLAGL = i286_membyte_read(seg, off + 0x16); | CPU_FLAGL = MEML_READ8(seg, off + 0x16); |
| CPU_AX = LOADINTELWORD(r.r_ax); | CPU_AX = LOADINTELWORD(r.r_ax); |
| CPU_BX = LOADINTELWORD(r.r_bx); | CPU_BX = LOADINTELWORD(r.r_bx); |
| CPU_CX = LOADINTELWORD(r.r_cx); | CPU_CX = LOADINTELWORD(r.r_cx); |
| Line 458 static void reg_store(UINT seg, UINT off | Line 458 static void reg_store(UINT seg, UINT off |
| STOREINTELWORD(r.r_di, CPU_DI); | STOREINTELWORD(r.r_di, CPU_DI); |
| STOREINTELWORD(r.r_si, CPU_SI); | STOREINTELWORD(r.r_si, CPU_SI); |
| STOREINTELWORD(r.r_ds, CPU_DS); | STOREINTELWORD(r.r_ds, CPU_DS); |
| i286_memstr_write(seg, off, &r, sizeof(r)); | MEML_WRITESTR(seg, off, &r, sizeof(r)); |
| i286_membyte_write(seg, off + 0x16, CPU_FLAGL); | MEML_WRITE8(seg, off + 0x16, CPU_FLAGL); |
| } | } |
| #endif | #endif |
| #if defined(SUPPORT_SASI) | #if defined(SUPPORT_IDEIO) || defined(SUPPORT_SASI) |
| void np2sysp_sasi(const void *arg1, long arg2) { | void np2sysp_sasi(const void *arg1, long arg2) { |
| UINT seg; | UINT seg; |