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| version 1.10, 2004/02/19 11:32:11 | version 1.11, 2004/02/21 16:35:31 |
|---|---|
| Line 12 | Line 12 |
| static struct { | static struct { |
| PMIXHDR hdr; | PMIXHDR hdr; |
| PMIXTRK trk[4]; | PMIXTRK trk[4]; |
| UINT rate; | |
| UINT enable; | |
| } amd98r; | } amd98r; |
| Line 103 static void pcmmake2(PMIXDAT *dat, UINT | Line 105 static void pcmmake2(PMIXDAT *dat, UINT |
| void amd98_initialize(UINT rate) { | void amd98_initialize(UINT rate) { |
| UINT i; | |
| ZeroMemory(&amd98r, sizeof(amd98r)); | ZeroMemory(&amd98r, sizeof(amd98r)); |
| amd98r.hdr.enable = 0x0f; | amd98r.rate = rate; |
| // bd | |
| pcmmake1(&amd98r.trk[0].data, rate, | |
| 24000, 889.0476190476, 0.9446717478); | |
| // lt | |
| pcmmake2(&amd98r.trk[1].data, rate, | |
| 6400, 172.9411764706, 0.8665145391, 0.9960000000); | |
| // ht | |
| pcmmake2(&amd98r.trk[2].data, rate, | |
| 9600, 213.0000000000, 0.8665145391, 0.9960000000); | |
| // sd | |
| pcmmake1(&amd98r.trk[3].data, rate, | |
| 12000, 255.4400000000, 0.8538230481); | |
| for (i=0; i<4; i++) { | |
| amd98r.trk[i].flag = PMIXFLAG_L | PMIXFLAG_R; | |
| amd98r.trk[i].volume = 1 << 12; | |
| } | |
| } | } |
| void amd98_deinitialize(void) { | void amd98_deinitialize(void) { |
| Line 130 void amd98_deinitialize(void) { | Line 114 void amd98_deinitialize(void) { |
| int i; | int i; |
| void *ptr; | void *ptr; |
| amd98r.hdr.enable = 0; | |
| for (i=0; i<4; i++) { | for (i=0; i<4; i++) { |
| ptr = amd98r.trk[i].data.sample; | ptr = amd98r.trk[i].data.sample; |
| amd98r.trk[i].data.sample = NULL; | amd98r.trk[i].data.sample = NULL; |
| Line 139 void amd98_deinitialize(void) { | Line 124 void amd98_deinitialize(void) { |
| } | } |
| } | } |
| static void amd98_rhythmload(void) { | |
| UINT i; | |
| if (!amd98r.hdr.enable) { | |
| TRACEOUT(("AMD98 Rhythm load")); | |
| amd98r.hdr.enable = 0x0f; | |
| // bd | |
| pcmmake1(&amd98r.trk[0].data, amd98r.rate, | |
| 24000, 889.0476190476, 0.9446717478); | |
| // lt | |
| pcmmake2(&amd98r.trk[1].data, amd98r.rate, | |
| 6400, 172.9411764706, 0.8665145391, 0.9960000000); | |
| // ht | |
| pcmmake2(&amd98r.trk[2].data, amd98r.rate, | |
| 9600, 213.0000000000, 0.8665145391, 0.9960000000); | |
| // sd | |
| pcmmake1(&amd98r.trk[3].data, amd98r.rate, | |
| 12000, 255.4400000000, 0.8538230481); | |
| for (i=0; i<4; i++) { | |
| amd98r.trk[i].flag = PMIXFLAG_L | PMIXFLAG_R; | |
| amd98r.trk[i].volume = 1 << 12; | |
| } | |
| } | |
| } | |
| // ---- | |
| static void amd98_rhythm(UINT map) { | static void amd98_rhythm(UINT map) { |
| PMIXTRK *trk; | PMIXTRK *trk; |
| Line 273 static void psgpanset(PSGGEN psg) { | Line 287 static void psgpanset(PSGGEN psg) { |
| void amd98_bind(void) { | void amd98_bind(void) { |
| amd98_rhythmload(); | |
| psgpanset(&psg1); | psgpanset(&psg1); |
| psgpanset(&psg2); | psgpanset(&psg2); |
| psgpanset(&psg3); | psgpanset(&psg3); |