--- np2/cbus/amd98.c	2004/02/19 11:32:11	1.10
+++ np2/cbus/amd98.c	2005/05/13 05:47:24	1.16
@@ -12,6 +12,8 @@
 static struct {
 	PMIXHDR	hdr;
 	PMIXTRK	trk[4];
+	UINT	rate;
+	UINT	enable;
 } amd98r;
 
 
@@ -103,26 +105,8 @@ static void pcmmake2(PMIXDAT *dat, UINT 
 
 void amd98_initialize(UINT rate) {
 
-	UINT	i;
-
 	ZeroMemory(&amd98r, sizeof(amd98r));
-	amd98r.hdr.enable = 0x0f;
-	// bd
-	pcmmake1(&amd98r.trk[0].data, rate,
-							24000, 889.0476190476, 0.9446717478);
-	// lt
-	pcmmake2(&amd98r.trk[1].data, rate,
-							6400, 172.9411764706, 0.8665145391, 0.9960000000);
-	// ht
-	pcmmake2(&amd98r.trk[2].data, rate,
-							9600, 213.0000000000, 0.8665145391, 0.9960000000);
-	// sd
-	pcmmake1(&amd98r.trk[3].data, rate,
-							12000, 255.4400000000, 0.8538230481);
-	for (i=0; i<4; i++) {
-		amd98r.trk[i].flag = PMIXFLAG_L | PMIXFLAG_R;
-		amd98r.trk[i].volume = 1 << 12;
-	}
+	amd98r.rate = rate;
 }
 
 void amd98_deinitialize(void) {
@@ -130,6 +114,7 @@ void amd98_deinitialize(void) {
 	int		i;
 	void	*ptr;
 
+	amd98r.hdr.enable = 0;
 	for (i=0; i<4; i++) {
 		ptr = amd98r.trk[i].data.sample;
 		amd98r.trk[i].data.sample = NULL;
@@ -139,6 +124,35 @@ void amd98_deinitialize(void) {
 	}
 }
 
+static void amd98_rhythmload(void) {
+
+	UINT	i;
+
+	if (!amd98r.hdr.enable) {
+		TRACEOUT(("AMD98 Rhythm load"));
+		amd98r.hdr.enable = 0x0f;
+		// bd
+		pcmmake1(&amd98r.trk[0].data, amd98r.rate,
+							24000, 889.0476190476, 0.9446717478);
+		// lt
+		pcmmake2(&amd98r.trk[1].data, amd98r.rate,
+							6400, 172.9411764706, 0.8665145391, 0.9960000000);
+		// ht
+		pcmmake2(&amd98r.trk[2].data, amd98r.rate,
+							9600, 213.0000000000, 0.8665145391, 0.9960000000);
+		// sd
+		pcmmake1(&amd98r.trk[3].data, amd98r.rate,
+							12000, 255.4400000000, 0.8538230481);
+		for (i=0; i<4; i++) {
+			amd98r.trk[i].flag = PMIXFLAG_L | PMIXFLAG_R;
+			amd98r.trk[i].volume = 1 << 12;
+		}
+	}
+}
+
+
+// ----
+
 static void amd98_rhythm(UINT map) {
 
 	PMIXTRK	*trk;
@@ -165,12 +179,10 @@ static void amd98_rhythm(UINT map) {
 
 // ----
 
-static void setamd98event(BOOL absolute) {
-
-	SINT32	cnt;
+static void setamd98event(UINT32 cnt, BOOL absolute) {
 
-	if (pit.value[3] > 8) {						// 根拠なし
-		cnt = pccore.multiple * pit.value[3];
+	if (cnt > 8) {								// 根拠なし
+		cnt *= pccore.multiple;
 	}
 	else {
 		cnt = pccore.multiple << 16;
@@ -183,10 +195,13 @@ static void setamd98event(BOOL absolute)
 
 void amd98int(NEVENTITEM item) {
 
+	PITCH	pitch;
+
 	if (item->flag & NEVENT_SETEVENT) {
-		if ((pit.mode[3] & 0x0c) == 0x04) {
+		pitch = pit.ch + 4;
+		if ((pitch->ctrl & 0x0c) == 0x04) {
 			// レートジェネレータ
-			setamd98event(NEVENT_RELATIVE);
+			setamd98event(pitch->value, NEVENT_RELATIVE);
 		}
 	}
 	pic_setirq(0x0d);
@@ -198,22 +213,25 @@ void amd98int(NEVENTITEM item) {
 
 static void IOOUTCALL amd_od8(UINT port, REG8 dat) {
 
-	opn.opnreg = dat;
+	opn.addr = dat;
 	(void)port;
 }
 
 static void IOOUTCALL amd_od9(UINT port, REG8 dat) {
 
-	opn.extreg = dat;
+	opn.addr2 = dat;
 	(void)port;
 }
 
 static void IOOUTCALL amd_oda(UINT port, REG8 dat) {
 
-	if (opn.opnreg < 0x0e) {
-		psggen_setreg(&psg1, opn.opnreg, dat);
+	UINT	addr;
+
+	addr = opn.addr;
+	if (addr < 0x0e) {
+		psggen_setreg(&psg1, addr, dat);
 	}
-	else if (opn.opnreg == 0x0f) {
+	else if (addr == 0x0f) {
 		psg1.reg.io2 = dat;
 	}
 	(void)port;
@@ -221,20 +239,21 @@ static void IOOUTCALL amd_oda(UINT port,
 
 static void IOOUTCALL amd_odb(UINT port, REG8 dat) {
 
-	if (opn.extreg < 0x0e) {
-		psggen_setreg(&psg2, opn.extreg, dat);
+	UINT	addr;
+
+	addr = opn.addr2;
+	if (addr < 0x0e) {
+		psggen_setreg(&psg2, addr, dat);
 	}
-	else if (opn.extreg == 0x0f) {
+	else if (addr == 0x0f) {
 		REG8 b;
 		b = psg2.reg.io2;
 		if ((b & 1) > (dat & 1)) {
 			b &= 0xc2;
 			if (b == 0x42) {
-//				TRACEOUT(0xfff0, psg_1.reg.io2);
 				amd98.psg3reg = psg1.reg.io2;
 			}
 			else if (b == 0x40) {
-//				TRACEOUT(0xfff1, psg_1.reg.io2);
 				if (amd98.psg3reg < 0x0e) {
 					psggen_setreg(&psg3, amd98.psg3reg, psg1.reg.io2);
 				}
@@ -250,17 +269,59 @@ static void IOOUTCALL amd_odb(UINT port,
 
 static void IOOUTCALL amd_odc(UINT port, REG8 dat) {
 
-	pit_setcount(3, dat);
-	setamd98event(NEVENT_ABSOLUTE);
+	PITCH	pitch;
+
+	pitch = pit.ch + 4;
+	if (pit_setcount(pitch, dat)) {
+		return;
+	}
+	setamd98event(pitch->value, NEVENT_ABSOLUTE);
 	(void)port;
 }
 
 static void IOOUTCALL amd_ode(UINT port, REG8 dat) {
 
-	pit_setflag(3, dat);
+	pit_setflag(pit.ch + 4, dat);
+	(void)port;
+}
+
+static REG8 IOINPCALL amd_ida(UINT port) {
+
+	UINT	addr;
+
+	addr = opn.addr;
+	if (addr < 0x0e) {
+		return(psggen_getreg(&psg1, addr));
+	}
+	else if (addr == 0x0f) {
+		return(psg1.reg.io2);
+	}
 	(void)port;
+	return(0xff);
 }
 
+static REG8 IOINPCALL amd_idb(UINT port) {
+
+	UINT	addr;
+
+	addr = opn.addr2;
+	if (addr < 0x0e) {
+		return(psggen_getreg(&psg2, addr));
+	}
+	else if (addr == 0x0f) {
+		return(psg2.reg.io2);
+	}
+	(void)port;
+	return(0xff);
+}
+
+#if defined(TRACE)
+static REG8 IOINPCALL amd_inp(UINT port) {
+
+	TRACEOUT(("amd inp - %.4x", port));
+	return(0xff);
+}
+#endif
 
 // ----
 
@@ -273,6 +334,8 @@ static void psgpanset(PSGGEN psg) {
 
 void amd98_bind(void) {
 
+	amd98_rhythmload();
+
 	psgpanset(&psg1);
 	psgpanset(&psg2);
 	psgpanset(&psg3);
@@ -289,5 +352,14 @@ void amd98_bind(void) {
 	iocore_attachout(0xdb, amd_odb);
 	iocore_attachout(0xdc, amd_odc);
 	iocore_attachout(0xde, amd_ode);
+
+	iocore_attachinp(0xda, amd_ida);
+	iocore_attachinp(0xdb, amd_idb);
+#if defined(TRACE)
+	iocore_attachinp(0xd8, amd_inp);
+	iocore_attachinp(0xd9, amd_inp);
+	iocore_attachinp(0xdc, amd_inp);
+	iocore_attachinp(0xde, amd_inp);
+#endif
 }