File:
[RetroPC.NET] /
np2 /
generic /
unasmop8.tbl
Revision
1.2:
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Sun Mar 7 11:37:40 2004 JST (21 years, 7 months ago) by
yui
Branches:
MAIN
CVS tags:
VER_0_82_x64,
VER_0_82,
VER_0_81A,
VER_0_81,
VER_0_80,
VER_0_79,
VER_0_78,
VER_0_77,
VER_0_76,
VER_0_75,
HEAD
fix unasm (CR,TR,DR) (T.Yui)
static const UINT32 op8tbl[0x100] = {
// 00
OP_T3(OP3_0f00),
OP_T3(OP3_0f01),
OP_WE(RSTR_LAR, OP_REG, OP_EA, 0),
OP_WE(RSTR_LSL, OP_REG, OP_EA, 0),
OP_ER,
OP_F0(RSTR_LOADALL),
OP_F0(RSTR_CLTS),
OP_F0(RSTR_LOADALL),
OP_F0(RSTR_INVD),
OP_F0(RSTR_WBINVD),
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
// 10
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
// 20
OP_Fe('c', OP1_REx),
OP_Fe('d', OP1_REx),
OP_Fe('c', OP1_ExR),
OP_Fe('d', OP1_ExR),
OP_Fe('t', OP1_REx),
OP_ER,
OP_Fe('t', OP1_ExR),
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
// 30
OP_F0(RSTR_WRMSR),
OP_F0(RSTR_RDTSC),
OP_F0(RSTR_RDMSR),
OP_F0(RSTR_RDPMC),
OP_F0(RSTR_SYSENTER),
OP_F0(RSTR_SYSEXIT),
OP_ER,
OP_ER,
OP_F0(RSTR_SMINT),
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
// 40
OP_WE(RSTR_CMCC+0, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+1, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+2, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+3, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+4, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+5, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+6, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+7, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+8, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+9, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+10, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+11, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+12, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+13, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+14, OP_REG, OP_EA, 0),
OP_WE(RSTR_CMCC+15, OP_REG, OP_EA, 0),
// 50
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
// 60
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
// 70
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
// 80
OP_F1(RSTR_JCC+0, OP1_NEAR),
OP_F1(RSTR_JCC+1, OP1_NEAR),
OP_F1(RSTR_JCC+2, OP1_NEAR),
OP_F1(RSTR_JCC+3, OP1_NEAR),
OP_F1(RSTR_JCC+4, OP1_NEAR),
OP_F1(RSTR_JCC+5, OP1_NEAR),
OP_F1(RSTR_JCC+6, OP1_NEAR),
OP_F1(RSTR_JCC+7, OP1_NEAR),
OP_F1(RSTR_JCC+8, OP1_NEAR),
OP_F1(RSTR_JCC+9, OP1_NEAR),
OP_F1(RSTR_JCC+10, OP1_NEAR),
OP_F1(RSTR_JCC+11, OP1_NEAR),
OP_F1(RSTR_JCC+12, OP1_NEAR),
OP_F1(RSTR_JCC+13, OP1_NEAR),
OP_F1(RSTR_JCC+14, OP1_NEAR),
OP_F1(RSTR_JCC+15, OP1_NEAR),
// 90
OP_BE(RSTR_STCC+0, OP_EA, 0, 0),
OP_BE(RSTR_STCC+1, OP_EA, 0, 0),
OP_BE(RSTR_STCC+2, OP_EA, 0, 0),
OP_BE(RSTR_STCC+3, OP_EA, 0, 0),
OP_BE(RSTR_STCC+4, OP_EA, 0, 0),
OP_BE(RSTR_STCC+5, OP_EA, 0, 0),
OP_BE(RSTR_STCC+6, OP_EA, 0, 0),
OP_BE(RSTR_STCC+7, OP_EA, 0, 0),
OP_BE(RSTR_STCC+8, OP_EA, 0, 0),
OP_BE(RSTR_STCC+9, OP_EA, 0, 0),
OP_BE(RSTR_STCC+10, OP_EA, 0, 0),
OP_BE(RSTR_STCC+11, OP_EA, 0, 0),
OP_BE(RSTR_STCC+12, OP_EA, 0, 0),
OP_BE(RSTR_STCC+13, OP_EA, 0, 0),
OP_BE(RSTR_STCC+14, OP_EA, 0, 0),
OP_BE(RSTR_STCC+15, OP_EA, 0, 0),
// a0
OP_F1(RSTR_PUSH, OP_SEG),
OP_F1(RSTR_POP, OP_SEG),
OP_F0(RSTR_CPUID),
OP_WE(RSTR_BT, OP_EA, OP_REG, 0),
OP_WE(RSTR_SHLD, OP_EA, OP_REG, OP_I8),
OP_WE(RSTR_SHLD, OP_EA, OP_REG, OP_CL),
OP_WE(RSTR_XBTS, OP_EA, OP_REG, 0), // 486 cmpxchg
OP_WE(RSTR_IBTS, OP_REG, OP_EA, 0), // 486 cmpxchg
OP_F1(RSTR_PUSH, OP_SEG),
OP_F1(RSTR_POP, OP_SEG),
OP_F0(RSTR_RSM),
OP_WE(RSTR_BTS, OP_EA, OP_REG, 0),
OP_WE(RSTR_SHRD, OP_EA, OP_REG, OP_I8),
OP_WE(RSTR_SHRD, OP_EA, OP_REG, OP_CL),
OP_ER,
OP_WE(RSTR_IMUL, OP_REG, OP_EA, 0),
// b0
OP_BE(RSTR_CMPXCHG, OP_EA, OP_REG, 0),
OP_WE(RSTR_CMPXCHG, OP_EA, OP_REG, 0),
OP_WE(RSTR_LSS, OP_REG, OP_EA, 0),
OP_WE(RSTR_BTR, OP_EA, OP_REG, 0),
OP_WE(RSTR_LFS, OP_REG, OP_EA, 0),
OP_WE(RSTR_LGS, OP_REG, OP_EA, 0),
OP_WE(RSTR_MOVZX, OE_MX0, OP_PEA, 0),
OP_WE(RSTR_MOVZX, OE_MX1, OP_PEA, 0),
OP_ER,
OP_ER,
OP_T3(OP3_0fba),
OP_WE(RSTR_BTC, OP_EA, OP_REG, 0),
OP_WE(RSTR_BSF, OP_EA, OP_REG, 0),
OP_WE(RSTR_BSR, OP_EA, OP_REG, 0),
OP_WE(RSTR_MOVSX, OE_MX0, OP_PEA, 0),
OP_WE(RSTR_MOVSX, OE_MX1, OP_PEA, 0),
// c0
OP_BE(RSTR_XADD, OP_EA, OP_REG, 0),
OP_WE(RSTR_XADD, OP_EA, OP_REG, 0),
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_ER,
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
OP_W_(RSTR_BSWAP, OP_MR, 0, 0),
// d0
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
// e0
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
// f0
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
OP_ER, OP_ER, OP_ER, OP_ER,
};
RetroPC.NET-CVS <cvs@retropc.net>