--- np2/i286a/cpucore.h 2003/12/20 11:49:47 1.2 +++ np2/i286a/cpucore.h 2004/01/05 15:47:18 1.8 @@ -1,8 +1,8 @@ //---------------------------------------------------------------------------- // -// i286c : 80286 Engine for Pentium ver0.05 +// i286a : 80286 Engine for ARM ver0.01 // -// Copyright by Yui/Studio Milmake 1999-2003 +// Copyright by Yui/Studio Milmake 2003 // //---------------------------------------------------------------------------- @@ -11,6 +11,10 @@ #if defined(CPUCORE_IA32) #error : not support CPUCORE_IA32 #endif +#if !defined(BYTESEX_LITTLE) +#error : not support !BYTESEX_LITTLE +#endif + #if !defined(CPUDEBUG) enum { @@ -37,6 +41,13 @@ enum { }; enum { + MSW_PE = 0x0001, + MSW_MP = 0x0002, + MSW_EM = 0x0004, + MSW_TS = 0x0008 +}; + +enum { CPUTYPE_V30 = 0x01 }; @@ -133,7 +144,7 @@ typedef struct { UINT16 limit; UINT16 base; UINT8 base24; - UINT8 reserved; + UINT8 ar; } I286DTR; typedef struct { @@ -141,43 +152,43 @@ typedef struct { I286REG8 b; I286REG16 w; } r; - SINT32 remainclock; - SINT32 baseclock; - UINT32 clock; - UINT32 adrsmask; // ver0.72 UINT32 es_base; UINT32 cs_base; UINT32 ss_base; UINT32 ds_base; UINT32 ss_fix; UINT32 ds_fix; + UINT32 adrsmask; // ver0.72 UINT16 prefix; UINT8 trap; - UINT8 cpu_type; - UINT32 ____pf_semaphore; // ج¤؛بحر - UINT32 ____repbak; // ج¤؛بحر - UINT32 inport; - UINT32 ovflag; + UINT8 resetreq; // ver0.72 I286DTR GDTR; - I286DTR IDTR; UINT16 MSW; - UINT8 resetreq; // ver0.72 + I286DTR IDTR; + UINT16 LDTR; // ver0.73 + I286DTR LDTRC; + UINT16 TR; + I286DTR TRC; + UINT8 padding[2]; + + UINT8 cpu_type; UINT8 itfbank; // ver0.72 + UINT16 ram_d0; + SINT32 remainclock; + SINT32 baseclock; + UINT32 clock; } I286STAT; typedef struct { // for ver0.73 BYTE *ext; UINT32 extsize; + UINT32 inport; #if defined(CPUSTRUC_MEMWAIT) UINT8 tramwait; UINT8 vramwait; UINT8 grcgwait; UINT8 padding; #endif -#if defined(CPUSTRUC_FONTPTR) - BYTE *fontlow; - BYTE *fonthigh; -#endif } I286EXT; typedef struct { @@ -191,19 +202,16 @@ typedef struct { extern "C" { #endif -extern I286CORE i286core; +extern I286CORE i286acore; extern const UINT8 iflags[]; -void i286c_initialize(void); -void i286c_reset(void); +void i286a_reset(void); +void i286a_shut(void); -void CPUCALL i286c_interrupt(REG8 vect); +void CPUCALL i286a_interrupt(REG8 vect); -void i286c(void); -void i286c_step(void); - -void v30c(void); -void v30c_step(void); +void i286a(void); +void i286a_step(void); #ifdef __cplusplus } @@ -212,76 +220,77 @@ void v30c_step(void); // ---- macros -#define mem i286core.m - -#define CPU_STATSAVE i286core.s +#define mem i286acore.m -#define CPU_AX i286core.s.r.w.ax -#define CPU_BX i286core.s.r.w.bx -#define CPU_CX i286core.s.r.w.cx -#define CPU_DX i286core.s.r.w.dx -#define CPU_SI i286core.s.r.w.si -#define CPU_DI i286core.s.r.w.di -#define CPU_BP i286core.s.r.w.bp -#define CPU_SP i286core.s.r.w.sp -#define CPU_CS i286core.s.r.w.cs -#define CPU_DS i286core.s.r.w.ds -#define CPU_ES i286core.s.r.w.es -#define CPU_SS i286core.s.r.w.ss -#define CPU_IP i286core.s.r.w.ip - -#define ES_BASE i286core.s.es_base -#define CS_BASE i286core.s.cs_base -#define SS_BASE i286core.s.ss_base -#define DS_BASE i286core.s.ds_base - -#define CPU_AL i286core.s.r.b.al -#define CPU_BL i286core.s.r.b.bl -#define CPU_CL i286core.s.r.b.cl -#define CPU_DL i286core.s.r.b.dl -#define CPU_AH i286core.s.r.b.ah -#define CPU_BH i286core.s.r.b.bh -#define CPU_CH i286core.s.r.b.ch -#define CPU_DH i286core.s.r.b.dh - -#define CPU_FLAG i286core.s.r.w.flag -#define CPU_FLAGL i286core.s.r.b.flag_l - -#define CPU_REMCLOCK i286core.s.remainclock -#define CPU_BASECLOCK i286core.s.baseclock -#define CPU_CLOCK i286core.s.clock -#define CPU_ADRSMASK i286core.s.adrsmask -#define CPU_RESETREQ i286core.s.resetreq -#define CPU_ITFBANK i286core.s.itfbank -#define CPU_INPADRS i286core.s.inport +#define CPU_STATSAVE i286acore.s -#define CPU_EXTMEM i286core.e.ext -#define CPU_EXTMEMSIZE i286core.e.extsize +#define CPU_AX i286acore.s.r.w.ax +#define CPU_BX i286acore.s.r.w.bx +#define CPU_CX i286acore.s.r.w.cx +#define CPU_DX i286acore.s.r.w.dx +#define CPU_SI i286acore.s.r.w.si +#define CPU_DI i286acore.s.r.w.di +#define CPU_BP i286acore.s.r.w.bp +#define CPU_SP i286acore.s.r.w.sp +#define CPU_CS i286acore.s.r.w.cs +#define CPU_DS i286acore.s.r.w.ds +#define CPU_ES i286acore.s.r.w.es +#define CPU_SS i286acore.s.r.w.ss +#define CPU_IP i286acore.s.r.w.ip + +#define ES_BASE i286acore.s.es_base +#define CS_BASE i286acore.s.cs_base +#define SS_BASE i286acore.s.ss_base +#define DS_BASE i286acore.s.ds_base + +#define CPU_AL i286acore.s.r.b.al +#define CPU_BL i286acore.s.r.b.bl +#define CPU_CL i286acore.s.r.b.cl +#define CPU_DL i286acore.s.r.b.dl +#define CPU_AH i286acore.s.r.b.ah +#define CPU_BH i286acore.s.r.b.bh +#define CPU_CH i286acore.s.r.b.ch +#define CPU_DH i286acore.s.r.b.dh + +#define CPU_FLAG i286acore.s.r.w.flag +#define CPU_FLAGL i286acore.s.r.b.flag_l + +#define SS_FIX i286acore.s.ss_fix +#define DS_FIX i286acore.s.ds_fix + +#define CPU_REMCLOCK i286acore.s.remainclock +#define CPU_BASECLOCK i286acore.s.baseclock +#define CPU_CLOCK i286acore.s.clock +#define CPU_ADRSMASK i286acore.s.adrsmask +#define CPU_MSW i286acore.s.MSW +#define CPU_RESETREQ i286acore.s.resetreq +#define CPU_ITFBANK i286acore.s.itfbank + +#define CPU_EXTMEM i286acore.e.ext +#define CPU_EXTMEMSIZE i286acore.e.extsize +#define CPU_INPADRS i286acore.e.inport -#define CPU_TYPE i286core.s.cpu_type +#define CPU_TYPE i286acore.s.cpu_type #if defined(CPUSTRUC_MEMWAIT) -#define MEMWAIT_TRAM i286core.e.tramwait -#define MEMWAIT_VRAM i286core.e.vramwait -#define MEMWAIT_GRCG i286core.e.grcgwait -#endif -#if defined(CPUSTRUC_FONTPTR) -#define FONTPTR_LOW i286core.e.fontlow -#define FONTPTR_HIGH i286core.e.fonthigh +#define MEMWAIT_TRAM i286acore.e.tramwait +#define MEMWAIT_VRAM i286acore.e.vramwait +#define MEMWAIT_GRCG i286acore.e.grcgwait #endif -#define CPU_isDI (!(i286core.s.r.w.flag & I_FLAG)) -#define CPU_isEI (i286core.s.r.w.flag & I_FLAG) -#define CPU_CLI i286core.s.r.w.flag &= ~I_FLAG; \ - i286core.s.trap = 0; -#define CPU_STI i286core.s.r.w.flag |= I_FLAG; \ - i286core.s.trap = (i286core.s.r.w.flag >> 8) & 1; +#define CPU_isDI (!(i286acore.s.r.w.flag & I_FLAG)) +#define CPU_isEI (i286acore.s.r.w.flag & I_FLAG) +#define CPU_CLI i286acore.s.r.w.flag &= ~I_FLAG; \ + i286acore.s.trap = 0; +#define CPU_STI i286acore.s.r.w.flag |= I_FLAG; \ + i286acore.s.trap = (i286acore.s.r.w.flag >> 8) & 1; -#define CPU_INITIALIZE i286c_initialize -#define CPU_RESET i286c_reset +#define CPU_INITIALIZE() +#define CPU_RESET i286a_reset #define CPU_CLEARPREFETCH() -#define CPU_INTERRUPT(v) i286c_interrupt(v) -#define CPU_EXEC i286c -#define CPU_EXECV30 v30c +#define CPU_INTERRUPT(v) i286a_interrupt(v) +#define CPU_EXEC i286a +#define CPU_EXECV30 i286a +#define CPU_SHUT i286a_shut