--- np2/i286a/cpucore.h	2003/12/22 07:41:15	1.4
+++ np2/i286a/cpucore.h	2004/01/07 06:53:47	1.9
@@ -11,6 +11,10 @@
 #if defined(CPUCORE_IA32)
 #error : not support CPUCORE_IA32
 #endif
+#if !defined(BYTESEX_LITTLE)
+#error : not support !BYTESEX_LITTLE
+#endif
+
 
 #if !defined(CPUDEBUG)
 enum {
@@ -37,6 +41,13 @@ enum {
 };
 
 enum {
+	MSW_PE			= 0x0001,
+	MSW_MP			= 0x0002,
+	MSW_EM			= 0x0004,
+	MSW_TS			= 0x0008
+};
+
+enum {
 	CPUTYPE_V30		= 0x01
 };
 
@@ -133,7 +144,7 @@ typedef struct {
 	UINT16	limit;
 	UINT16	base;
 	UINT8	base24;
-	UINT8	reserved;
+	UINT8	ar;
 } I286DTR;
 
 typedef struct {
@@ -141,33 +152,37 @@ typedef struct {
 		I286REG8	b;
 		I286REG16	w;
 	}		r;
-	SINT32	remainclock;
-	SINT32	baseclock;
-	UINT32	clock;
-	UINT32	adrsmask;						// ver0.72
 	UINT32	es_base;
 	UINT32	cs_base;
 	UINT32	ss_base;
 	UINT32	ds_base;
 	UINT32	ss_fix;
 	UINT32	ds_fix;
+	UINT32	adrsmask;						// ver0.72
 	UINT16	prefix;
-	UINT8	trap;
-	UINT8	cpu_type;
-	UINT32	____pf_semaphore;				// ج¤؛بحر
-	UINT32	____repbak;						// ج¤؛بحر
-	UINT32	inport;
-	UINT32	ovflag;
+	UINT8	__trap;
+	UINT8	resetreq;						// ver0.72
 	I286DTR	GDTR;
-	I286DTR	IDTR;
 	UINT16	MSW;
-	UINT8	resetreq;						// ver0.72
+	I286DTR	IDTR;
+	UINT16	LDTR;							// ver0.73
+	I286DTR	LDTRC;
+	UINT16	TR;
+	I286DTR	TRC;
+	UINT8	padding[2];
+
+	UINT8	cpu_type;
 	UINT8	itfbank;						// ver0.72
+	UINT16	ram_d0;
+	SINT32	remainclock;
+	SINT32	baseclock;
+	UINT32	clock;
 } I286STAT;
 
 typedef struct {							// for ver0.73
 	BYTE	*ext;
 	UINT32	extsize;
+	UINT32	inport;
 #if defined(CPUSTRUC_MEMWAIT)
 	UINT8	tramwait;
 	UINT8	vramwait;
@@ -191,6 +206,7 @@ extern	I286CORE	i286acore;
 extern	const UINT8	iflags[];
 
 void i286a_reset(void);
+void i286a_shut(void);
 
 void CPUCALL i286a_interrupt(REG8 vect);
 
@@ -239,16 +255,21 @@ void i286a_step(void);
 #define	CPU_FLAG		i286acore.s.r.w.flag
 #define	CPU_FLAGL		i286acore.s.r.b.flag_l
 
+#define	SS_FIX			i286acore.s.ss_fix
+#define	DS_FIX			i286acore.s.ds_fix
+
 #define	CPU_REMCLOCK	i286acore.s.remainclock
 #define	CPU_BASECLOCK	i286acore.s.baseclock
 #define	CPU_CLOCK		i286acore.s.clock
 #define	CPU_ADRSMASK	i286acore.s.adrsmask
+#define	CPU_MSW			i286acore.s.MSW
 #define	CPU_RESETREQ	i286acore.s.resetreq
 #define	CPU_ITFBANK		i286acore.s.itfbank
-#define	CPU_INPADRS		i286acore.s.inport
+#define	CPU_RAM_D000	i286acore.s.ram_d0
 
 #define	CPU_EXTMEM		i286acore.e.ext
 #define	CPU_EXTMEMSIZE	i286acore.e.extsize
+#define	CPU_INPADRS		i286acore.e.inport
 
 #define	CPU_TYPE		i286acore.s.cpu_type
 
@@ -261,10 +282,8 @@ void i286a_step(void);
 
 #define	CPU_isDI		(!(i286acore.s.r.w.flag & I_FLAG))
 #define	CPU_isEI		(i286acore.s.r.w.flag & I_FLAG)
-#define	CPU_CLI			i286acore.s.r.w.flag &= ~I_FLAG;					\
-						i286acore.s.trap = 0;
-#define	CPU_STI			i286acore.s.r.w.flag |= I_FLAG;						\
-						i286acore.s.trap = (i286acore.s.r.w.flag >> 8) & 1;
+#define	CPU_CLI			i286acore.s.r.w.flag &= ~I_FLAG;
+#define	CPU_STI			i286acore.s.r.w.flag |= I_FLAG;
 
 #define	CPU_INITIALIZE()
 #define	CPU_RESET			i286a_reset
@@ -272,4 +291,5 @@ void i286a_step(void);
 #define	CPU_INTERRUPT(v)	i286a_interrupt(v)
 #define	CPU_EXEC			i286a
 #define	CPU_EXECV30			i286a
+#define	CPU_SHUT			i286a_shut