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| version 1.4, 2003/12/17 10:41:06 | version 1.20, 2004/07/17 20:43:02 |
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| Line 12 I_FLAG equ &0200 | Line 12 I_FLAG equ &0200 |
| D_FLAG equ &0400 | D_FLAG equ &0400 |
| O_FLAG equ &0800 | O_FLAG equ &0800 |
| CPU_REG equ 0 - 112 | MSW_PE equ &0001 |
| CPU_REMAINCLOCK equ 28 - 112 | MSW_MP equ &0002 |
| ; cpu_baseclock equ 32 - 112 | MSW_EM equ &0004 |
| ; cpu_clock equ 36 - 112 | MSW_TS equ &0008 |
| ; cpu_adrsmask equ 40 - 112 | |
| CPU_ES_BASE equ 44 - 112 | CPU_SIZE equ (104 + 32) |
| CPU_CS_BASE equ 48 - 112 | CPU_STAT equ (0 - CPU_SIZE) |
| CPU_SS_BASE equ 52 - 112 | CPU_EXT equ (104 - CPU_SIZE) |
| CPU_DS_BASE equ 56 - 112 | |
| CPU_SS_FIX equ 60 - 112 | CPU_REG equ CPU_STAT + 0 |
| CPU_DS_FIX equ 64 - 112 | CPU_SEG equ CPU_STAT + 16 |
| ; cpu_prefix equ 68 - 112 | CPU_ES_BASE equ CPU_STAT + 28 |
| CPU_TRAP equ 70 - 112 | CPU_CS_BASE equ CPU_STAT + 32 |
| ; cpu_type equ 71 - 112 | CPU_SS_BASE equ CPU_STAT + 36 |
| ; cpu_pf_semaphore equ 72 - 112 | CPU_DS_BASE equ CPU_STAT + 40 |
| ; cpu_repbak equ 76 - 112 | CPU_SS_FIX equ CPU_STAT + 44 |
| ; cpu_inport equ 80 - 112 | CPU_DS_FIX equ CPU_STAT + 48 |
| ; cpu_ovflag equ 84 - 112 | CPU_ADRSMASK equ CPU_STAT + 52 |
| CPU_GDTR equ 88 - 112 | CPU_PREFIX equ CPU_STAT + 56 |
| CPU_IDTR equ 94 - 112 | ; cpu_resetreq equ CPU_STAT + 57 |
| ; cpu_MSW equ 100 - 112 | CPU_GDTR equ CPU_STAT + 58 |
| ; cpu_resetreq equ 102 - 112 | CPU_MSW equ CPU_STAT + 64 |
| ; cpu_itfbank equ 103 - 112 | CPU_IDTR equ CPU_STAT + 66 |
| ; cpu_extmem equ 104 - 112 | CPU_LDTR equ CPU_STAT + 72 |
| ; cpu_extmemsize equ 108 - 112 | CPU_LDTRC equ CPU_STAT + 74 |
| ; cpu_mainmem equ 112 - 112 | CPU_TR equ CPU_STAT + 80 |
| CPU_TRC equ CPU_STAT + 82 | |
| CPU_AL equ 0 - 112 | ; cpu_type equ CPU_STAT + 88 |
| CPU_AH equ 1 - 112 | CPU_ITFBANK equ CPU_STAT + 89 |
| CPU_CL equ 2 - 112 | ; cpu_ram_d0 equ CPU_STAT + 90 |
| CPU_CH equ 3 - 112 | CPU_REMAINCLOCK equ CPU_STAT + 92 |
| CPU_DL equ 4 - 112 | CPU_BASECLOCK equ CPU_STAT + 96 |
| CPU_DH equ 5 - 112 | ; cpu_clock equ CPU_STAT + 100 |
| CPU_BL equ 6 - 112 | ; cpu_stat_size equ 104 |
| CPU_BH equ 7 - 112 | |
| CPU_AL equ CPU_STAT + 0 | |
| CPU_AX equ 0 - 112 | CPU_AH equ CPU_STAT + 1 |
| CPU_CX equ 2 - 112 | CPU_CL equ CPU_STAT + 2 |
| CPU_DX equ 4 - 112 | CPU_CH equ CPU_STAT + 3 |
| CPU_BX equ 6 - 112 | CPU_DL equ CPU_STAT + 4 |
| CPU_SP equ 8 - 112 | CPU_DH equ CPU_STAT + 5 |
| CPU_BP equ 10 - 112 | CPU_BL equ CPU_STAT + 6 |
| CPU_SI equ 12 - 112 | CPU_BH equ CPU_STAT + 7 |
| CPU_DI equ 14 - 112 | |
| CPU_ES equ 16 - 112 | CPU_AX equ CPU_STAT + 0 |
| CPU_CS equ 18 - 112 | CPU_CX equ CPU_STAT + 2 |
| CPU_SS equ 20 - 112 | CPU_DX equ CPU_STAT + 4 |
| CPU_DS equ 22 - 112 | CPU_BX equ CPU_STAT + 6 |
| CPU_FLAG equ 24 - 112 | CPU_SP equ CPU_STAT + 8 |
| CPU_IP equ 26 - 112 | CPU_BP equ CPU_STAT + 10 |
| CPU_SI equ CPU_STAT + 12 | |
| CPU_DI equ CPU_STAT + 14 | |
| CPU_ES equ CPU_STAT + 16 | |
| CPU_CS equ CPU_STAT + 18 | |
| CPU_SS equ CPU_STAT + 20 | |
| CPU_DS equ CPU_STAT + 22 | |
| CPU_FLAG equ CPU_STAT + 24 | |
| CPU_IP equ CPU_STAT + 26 | |
| CPU_EXTMEM equ CPU_EXT + 0 | |
| CPU_EXTMEMSIZE equ CPU_EXT + 4 | |
| CPU_EMS equ CPU_EXT + 8 | |
| CPU_INPUT equ CPU_EXT + 24 | |
| MEMWAIT_TRAM equ CPU_EXT + 28 | |
| MEMWAIT_VRAM equ CPU_EXT + 29 | |
| MEMWAIT_GRCG equ CPU_EXT + 30 | |
| ; cpu_ext_size equ 32 | |
| MAX_PREFIX equ 8 | |
| MACRO | |
| $label CPUDBGS | |
| $label ;; str r7, [r9, #CPU_REMAINCLOCK] | |
| MEND | |
| MACRO | |
| $label CPUDBGL | |
| $label ;; ldr r7, [r9, #CPU_REMAINCLOCK] | |
| MEND | |
| MACRO | MACRO |
| $label CPUWORK $clock | $label CPUSVC |
| $label ldr r7, [r9, #CPU_REMAINCLOCK] | $label str r7, [r9, #CPU_REMAINCLOCK] |
| sub r7, r7, $clock | |
| str r7, [r9, #CPU_REMAINCLOCK] | |
| MEND | MEND |
| MACRO | MACRO |
| $label CREMSET $clock | $label CPULDC |
| $label mov r7, $clock | $label ldr r7, [r9, #CPU_REMAINCLOCK] |
| str r7, [r9, #CPU_REMAINCLOCK] | |
| MEND | MEND |
| MACRO | MACRO |
| $label CPUSV | $label CPUSVF |
| $label | $label str r8, [r9, #CPU_FLAG] |
| MEND | MEND |
| MACRO | MACRO |
| $label CPULD | $label CPULDF |
| $label | $label ldr r8, [r9, #CPU_FLAG] |
| MEND | MEND |
| MACRO | MACRO |
| $label GETPC8 | $label CPUSV |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label CPUSVF |
| add r0, r0, r8 lsr #16 | CPUSVC |
| bl i286_memoryread | |
| add r8, r8, #(1 << 16) | |
| MEND | MEND |
| MACRO | MACRO |
| $label GETPC16 | $label CPULD |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label CPULDF |
| add r0, r0, r8 lsr #16 | CPULDC |
| bl i286_memoryread_w | |
| add r8, r8, #(2 << 16) | |
| MEND | MEND |
| MACRO | MACRO |
| $label R8SRC $op, $out | $label CPUWORK $clock |
| $label and $out, $op, #3 | $label CPUDBGL |
| add $out, r9, $out lsl #1 | sub r7, r7, $clock |
| tst $op, #(1 << 2) | CPUDBGS |
| addne $out, $out, #1 | |
| MEND | |
| MACRO | |
| $label R8DST $op, $out | |
| $label and $out, $op, #(6 << 2) | |
| add $out, r9, $out lsr #2 | |
| tst $op, #(1 << 5) | |
| addne $out, $out, #1 | |
| MEND | MEND |
| MACRO | MACRO |
| $label EAREG8 $src | $label CPUWKS $clock |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label CPUDBGL |
| add r0, r0, r8 lsr #16 | subs r7, r7, $clock |
| bl i286_memoryread | CPUDBGS |
| add r8, r8, #(1 << 16) | |
| and $src, r0, #(6 << 2) | |
| add $src, r9, $src lsr #2 | |
| tst r0, #(1 << 5) | |
| addne $src, $src, #1 | |
| MEND | MEND |
| MACRO | MACRO |
| $label REG8EA $dst, $regclk, $memclk | $label CREMSET $clock |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label mov r7, $clock |
| add r0, r0, r8 lsr #16 | CPUDBGS |
| bl i286_memoryread | |
| add r8, r8, #(1 << 16) | |
| R8DST r0, $dst | |
| cmp r0, #&c0 | |
| bcc $label.1 | |
| CPUWORK $regclk | |
| R8SRC r0, r12 | |
| ldrb r0, [r12, #CPU_REG] | |
| b $label.2 | |
| $label.1 CPUWORK $memclk | |
| bl i286a_ea | |
| bl i286_memoryread | |
| $label.2 | |
| MEND | MEND |
| MACRO | MACRO |
| $label R16SRC $op, $out | $label NEXT_OPCODE |
| $label and $out, $op, #7 | $label CPUDBGL |
| add $out, r9, $out lsl #1 | cmp r7, #1 |
| movge pc, r11 | |
| ldr r0, [r9, #CPU_BASECLOCK] | |
| rsb r1, r7, #1 | |
| mov r7, #1 | |
| add r0, r0, r1 | |
| str r0, [r9, #CPU_BASECLOCK] | |
| CPUDBGS | |
| mov pc, r11 | |
| MEND | MEND |
| MACRO | MACRO |
| $label R16DST $op, $out | $label REMAIN_ADJUST $clk |
| $label and $out, $op, #(7 << 3) | $label CPUDBGL |
| add $out, r9, $out lsr #2 | cmp r7, $clk |
| moveq pc, r11 | |
| ldr r0, [r9, #CPU_BASECLOCK] | |
| rsb r1, r7, $clk | |
| mov r7, $clk | |
| add r0, r0, r1 | |
| str r0, [r9, #CPU_BASECLOCK] | |
| CPUDBGS | |
| mov pc, r11 | |
| MEND | MEND |
| MACRO | MACRO |
| $label EAREG16 $src | $label I286IRQCHECKTERM |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label CPUDBGL |
| add r0, r0, r8 lsr #16 | cmp r7, #0 |
| bl i286_memoryread | movle pc, r11 |
| add r8, r8, #(1 << 16) | ldr r0, [r9, #CPU_BASECLOCK] |
| and $src, r0, #(7 << 3) | mov r1, r7 |
| add $src, r9, $src lsr #2 | mov r7, #0 |
| sub r0, r0, r1 | |
| str r0, [r9, #CPU_BASECLOCK] | |
| CPUDBGS | |
| mov pc, r11 | |
| MEND | MEND |
| MACRO | MACRO |
| $label REG16EA $dst, $regclk, $memclk | $label ACCWORD $r, $l |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label tst $r, #1 |
| add r0, r0, r8 lsr #16 | bne $l |
| bl i286_memoryread | cmp $r, #I286_MEMWRITEMAX |
| add r8, r8, #(1 << 16) | bcs $l |
| R16DST r0, $dst | |
| cmp r0, #&c0 | |
| bcc $label.1 | |
| CPUWORK $regclk | |
| R16SRC r0, r12 | |
| ldrh r0, [r12, #CPU_REG] | |
| b $label.2 | |
| $label.1 CPUWORK $memclk | |
| bl i286a_ea | |
| bl i286_memoryread_w | |
| $label.2 | |
| MEND | MEND |
| END | END |