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version 1.2, 2003/12/17 10:41:06
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version 1.7, 2003/12/22 07:41:15
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Line 8
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Line 8
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| INCLUDE i286a.inc |
INCLUDE i286a.inc |
| IMPORT i286_memoryread |
IMPORT i286a_memoryread |
| IMPORT i286_memoryread_w |
IMPORT i286a_memoryread_w |
| |
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| EXPORT i286a_ea |
EXPORT i286a_ea |
| EXPORT i286a_lea |
EXPORT i286a_lea |
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Line 19
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Line 19
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| ; ---- calc_ea_dst |
; ---- calc_ea_dst |
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MACRO |
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$label EAR1 $r, $b |
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$label ldrh r1, [r9, $r] |
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ldr r2, [r9, $b] |
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add r0, r2, r1 |
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mov pc, lr |
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MEND |
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MACRO |
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$label EAR1D8 $r, $b |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread |
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ldrh r1, [r9, $r] |
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ldr r2, [r9, $b] |
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mov r3, r0 lsl #24 |
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mov r12, r1 lsl #16 |
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add r1, r12, r3 asr #8 |
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add r8, r8, #(1 << 16) |
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add r0, r2, r1 lsr #16 |
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mov pc, r4 |
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MEND |
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MACRO |
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$label EAR1D16 $r, $b |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread_w |
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ldrh r1, [r9, $r] |
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ldr r2, [r9, $b] |
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add r8, r8, #(2 << 16) |
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add r3, r1, r0 |
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bic r1, r3, #(1 << 16) |
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add r0, r1, r2 |
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mov pc, r4 |
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MEND |
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MACRO |
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$label EAR2 $r1, $r2, $b |
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$label ldrh r1, [r9, $r1] |
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ldrh r2, [r9, $r2] |
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ldr r3, [r9, $b] |
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add r12, r2, r1 |
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bic r12, r12, #(1 << 16) |
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add r0, r12, r3 |
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mov pc, lr |
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MEND |
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MACRO |
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$label EAR2D8 $r1, $r2, $b |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread |
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ldrh r1, [r9, $r1] |
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ldrh r2, [r9, $r2] |
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mov r12, r0 lsl #24 |
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ldr r3, [r9, $b] |
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mov r12, r12 asr #8 |
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add r12, r12, r1 lsl #16 |
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add r12, r12, r2 lsl #16 |
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add r8, r8, #(1 << 16) |
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add r0, r3, r12 lsr #16 |
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mov pc, r4 |
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MEND |
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MACRO |
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$label EAR2D16 $r1, $r2, $b |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread_w |
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ldrh r1, [r9, $r1] |
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ldrh r2, [r9, $r2] |
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ldr r3, [r9, $b] |
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add r12, r1, r0 |
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add r8, r8, #(2 << 16) |
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add r12, r12, r2 |
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bic r12, r12, #(3 << 16) |
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add r0, r12, r3 |
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mov pc, r4 |
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MEND |
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| i286a_ea and r1, r0, #(&18 << 3) |
i286a_ea and r1, r0, #(&18 << 3) |
| and r2, r0, #7 |
and r2, r0, #7 |
| add r3, pc, r1 lsr #1 |
add r3, pc, r1 lsr #1 |
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Line 51 i286a_ea and r1, r0, #(&18 << 3)
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Line 136 i286a_ea and r1, r0, #(&18 << 3)
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| b ea_bp_d16 |
b ea_bp_d16 |
| b ea_bx_d16 |
b ea_bx_d16 |
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| ea_bx_si ldrh r1, [r9, #CPU_BX] |
ea_bx_si EAR2 #CPU_BX, #CPU_SI, #CPU_DS_FIX |
| ldrh r2, [r9, #CPU_SI] |
ea_bx_si_d8 EAR2D8 #CPU_BX, #CPU_SI, #CPU_DS_FIX |
| ldr r0, [r9, #CPU_DS_FIX] |
ea_bx_si_d16 EAR2D16 #CPU_BX, #CPU_SI, #CPU_DS_FIX |
| add r3, r1, r2 |
ea_bx_di EAR2 #CPU_BX, #CPU_DI, #CPU_DS_FIX |
| bic r12, r3, #(1 << 16) |
ea_bx_di_d8 EAR2D8 #CPU_BX, #CPU_DI, #CPU_DS_FIX |
| add r0, r12, r0 |
ea_bx_di_d16 EAR2D16 #CPU_BX, #CPU_DI, #CPU_DS_FIX |
| mov pc, lr |
ea_bp_si EAR2 #CPU_BP, #CPU_SI, #CPU_SS_FIX |
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ea_bp_si_d8 EAR2D8 #CPU_BP, #CPU_SI, #CPU_SS_FIX |
| ea_bx_si_d8 mov r4, lr |
ea_bp_si_d16 EAR2D16 #CPU_BP, #CPU_SI, #CPU_SS_FIX |
| ldr r0, [r9, #CPU_CS_BASE] |
ea_bp_di EAR2 #CPU_BP, #CPU_DI, #CPU_SS_FIX |
| add r0, r0, r8 lsr #16 |
ea_bp_di_d8 EAR2D8 #CPU_BP, #CPU_DI, #CPU_SS_FIX |
| bl i286_memoryread |
ea_bp_di_d16 EAR2D16 #CPU_BP, #CPU_DI, #CPU_SS_FIX |
| ldrh r1, [r9, #CPU_BX] |
ea_si EAR1 #CPU_SI, #CPU_DS_FIX |
| ldrh r2, [r9, #CPU_SI] |
ea_si_d8 EAR1D8 #CPU_SI, #CPU_DS_FIX |
| ldr r3, [r9, #CPU_DS_FIX] |
ea_si_d16 EAR1D16 #CPU_SI, #CPU_DS_FIX |
| add r1, r1, r2 |
ea_di EAR1 #CPU_DI, #CPU_DS_FIX |
| mov r12, r0 lsl #24 |
ea_di_d8 EAR1D8 #CPU_DI, #CPU_DS_FIX |
| add r8, r8, #(1 << 16) |
ea_di_d16 EAR1D16 #CPU_DI, #CPU_DS_FIX |
| add r2, r1, r12 asr #24 |
ea_bx EAR1 #CPU_BX, #CPU_DS_FIX |
| mov r1, r2 lsl #16 |
ea_bx_d8 EAR1D8 #CPU_BX, #CPU_DS_FIX |
| add r0, r3, r1 lsr #16 |
ea_bx_d16 EAR1D16 #CPU_BX, #CPU_DS_FIX |
| mov pc, r4 |
ea_bp_d8 EAR1D8 #CPU_BP, #CPU_SS_FIX |
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ea_bp_d16 EAR1D16 #CPU_BP, #CPU_SS_FIX |
| ea_bx_si_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_BX] |
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| ldrh r2, [r9, #CPU_SI] |
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| ldr r3, [r9, #CPU_DS_FIX] |
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| add r12, r1, r2 |
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| add r8, r8, #(2 << 16) |
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| add r2, r12, r0 |
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| bic r1, r2, #(3 << 16) |
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| add r0, r1, r3 |
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| mov pc, r4 |
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| ea_bx_di ldrh r1, [r9, #CPU_BX] |
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| ldrh r2, [r9, #CPU_DI] |
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| ldr r0, [r9, #CPU_DS_FIX] |
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| add r3, r1, r2 |
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| bic r12, r3, #(1 << 16) |
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| add r0, r12, r0 |
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| mov pc, lr |
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| ea_bx_di_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_BX] |
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| ldrh r2, [r9, #CPU_DI] |
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| ldr r3, [r9, #CPU_DS_FIX] |
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| add r1, r1, r2 |
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| mov r12, r0 lsl #24 |
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| add r8, r8, #(1 << 16) |
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| add r2, r1, r12 asr #24 |
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| mov r1, r2 lsl #16 |
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| add r0, r3, r1 lsr #16 |
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| mov pc, r4 |
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| ea_bx_di_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_BX] |
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| ldrh r2, [r9, #CPU_DI] |
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| ldr r3, [r9, #CPU_DS_FIX] |
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| add r12, r1, r2 |
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| add r8, r8, #(2 << 16) |
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| add r2, r12, r0 |
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| bic r1, r2, #(3 << 16) |
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| add r0, r1, r3 |
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| mov pc, r4 |
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| ea_bp_si ldrh r1, [r9, #CPU_BP] |
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| ldrh r2, [r9, #CPU_SI] |
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| ldr r0, [r9, #CPU_SS_FIX] |
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| add r3, r1, r2 |
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| bic r12, r3, #(1 << 16) |
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| add r0, r12, r0 |
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| mov pc, lr |
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| ea_bp_si_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_BP] |
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| ldrh r2, [r9, #CPU_SI] |
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| ldr r3, [r9, #CPU_SS_FIX] |
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| add r1, r1, r2 |
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| mov r12, r0 lsl #24 |
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| add r8, r8, #(1 << 16) |
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| add r2, r1, r12 asr #24 |
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| mov r1, r2 lsl #16 |
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| add r0, r3, r1 lsr #16 |
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| mov pc, r4 |
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| ea_bp_si_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_BP] |
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| ldrh r2, [r9, #CPU_SI] |
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| ldr r3, [r9, #CPU_SS_FIX] |
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| add r12, r1, r2 |
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| add r8, r8, #(2 << 16) |
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| add r2, r12, r0 |
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| bic r1, r2, #(3 << 16) |
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| add r0, r1, r3 |
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| mov pc, r4 |
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| ea_bp_di ldrh r1, [r9, #CPU_BP] |
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| ldrh r2, [r9, #CPU_DI] |
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| ldr r0, [r9, #CPU_SS_FIX] |
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| add r3, r1, r2 |
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| bic r12, r3, #(1 << 16) |
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| add r0, r12, r0 |
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| mov pc, lr |
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| ea_bp_di_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_BP] |
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| ldrh r2, [r9, #CPU_DI] |
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| ldr r3, [r9, #CPU_SS_FIX] |
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| add r1, r1, r2 |
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| mov r12, r0 lsl #24 |
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| add r8, r8, #(1 << 16) |
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| add r2, r1, r12 asr #24 |
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| mov r1, r2 lsl #16 |
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| add r0, r3, r1 lsr #16 |
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| mov pc, r4 |
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| ea_bp_di_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_BP] |
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| ldrh r2, [r9, #CPU_DI] |
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| ldr r3, [r9, #CPU_SS_FIX] |
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| add r12, r1, r2 |
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| add r8, r8, #(2 << 16) |
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| add r2, r12, r0 |
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| bic r1, r2, #(3 << 16) |
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| add r0, r1, r3 |
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| mov pc, r4 |
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| ea_si ldrh r1, [r9, #CPU_SI] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| add r0, r1, r2 |
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| mov pc, lr |
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| ea_si_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_SI] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| mov r3, r0 lsl #24 |
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| mov r12, r1 lsl #16 |
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| add r8, r8, #(1 << 16) |
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| add r1, r12, r3, asr #8 |
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| add r0, r2, r1 lsr #16 |
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| mov pc, r4 |
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| ea_si_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_SI] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| add r8, r8, #(2 << 16) |
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| add r3, r0, r1 |
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| bic r1, r3, #(1 << 16) |
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| add r0, r1, r2 |
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| mov pc, r4 |
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| ea_di ldrh r1, [r9, #CPU_DI] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| add r0, r1, r2 |
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| mov pc, lr |
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| ea_di_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_DI] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| mov r3, r0 lsl #24 |
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| mov r12, r1 lsl #16 |
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| add r8, r8, #(1 << 16) |
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| add r1, r12, r3, asr #8 |
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| add r0, r2, r1 lsr #16 |
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| mov pc, r4 |
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| ea_di_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_DI] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| add r8, r8, #(2 << 16) |
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| add r3, r0, r1 |
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| bic r1, r3, #(1 << 16) |
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| add r0, r1, r2 |
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| mov pc, r4 |
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| ea_bx ldrh r1, [r9, #CPU_BX] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| add r0, r1, r2 |
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| mov pc, lr |
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| ea_bx_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_BX] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| mov r3, r0 lsl #24 |
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| mov r12, r1 lsl #16 |
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| add r8, r8, #(1 << 16) |
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| add r1, r12, r3, asr #8 |
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| add r0, r2, r1 lsr #16 |
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| mov pc, r4 |
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| ea_bx_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_BX] |
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| ldr r2, [r9, #CPU_DS_FIX] |
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| add r8, r8, #(2 << 16) |
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| add r3, r0, r1 |
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| bic r1, r3, #(1 << 16) |
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| add r0, r1, r2 |
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| mov pc, r4 |
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| |
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| ea_d16 mov r4, lr |
ea_d16 mov r4, lr |
| ldr r0, [r9, #CPU_CS_BASE] |
ldr r0, [r9, #CPU_CS_BASE] |
| add r0, r0, r8 lsr #16 |
add r0, r0, r8 lsr #16 |
| bl i286_memoryread_w |
bl i286a_memoryread_w |
| ldr r1, [r9, #CPU_DS_FIX] |
ldr r1, [r9, #CPU_DS_FIX] |
| add r8, r8, #(2 << 16) |
add r8, r8, #(2 << 16) |
| add r0, r0, r1 |
add r0, r0, r1 |
| mov pc, r4 |
mov pc, r4 |
| |
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| ea_bp_d8 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread |
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| ldrh r1, [r9, #CPU_BP] |
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| ldr r2, [r9, #CPU_SS_FIX] |
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| mov r3, r0 lsl #24 |
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| mov r12, r1 lsl #16 |
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| add r8, r8, #(1 << 16) |
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| add r1, r12, r3, asr #8 |
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| add r0, r2, r1 lsr #16 |
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| mov pc, r4 |
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| |
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| ea_bp_d16 mov r4, lr |
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| ldr r0, [r9, #CPU_CS_BASE] |
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| add r0, r0, r8 lsr #16 |
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| bl i286_memoryread_w |
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| ldrh r1, [r9, #CPU_BP] |
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| ldr r2, [r9, #CPU_SS_FIX] |
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| add r8, r8, #(2 << 16) |
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| add r3, r0, r1 |
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| bic r1, r3, #(1 << 16) |
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| add r0, r1, r2 |
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| mov pc, r4 |
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| ; ---- calc_lea |
; ---- calc_lea |
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MACRO |
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$label LER1 $r |
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$label ldrh r0, [r9, $r] |
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mov pc, lr |
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MEND |
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|
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MACRO |
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$label LER1D8 $r |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread |
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ldrh r1, [r9, $r] |
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add r8, r8, #(1 << 16) |
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tst r0, #&80 |
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orrne r0, r0, #&ff00 |
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add r0, r0, r1 |
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bic r0, r0, #(1 << 16) |
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mov pc, r4 |
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MEND |
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MACRO |
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$label LER1D16 $r |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread_w |
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ldrh r1, [r9, $r] |
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add r8, r8, #(2 << 16) |
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add r3, r1, r0 |
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bic r0, r3, #(1 << 16) |
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mov pc, r4 |
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MEND |
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|
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MACRO |
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$label LER2 $r1, $r2 |
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$label ldrh r1, [r9, $r1] |
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ldrh r2, [r9, $r2] |
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add r12, r2, r1 |
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bic r0, r12, #(1 << 16) |
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mov pc, lr |
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MEND |
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|
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MACRO |
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$label LER2D8 $r1, $r2 |
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$label ldr r0, [r9, #CPU_CS_BASE] |
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mov r4, lr |
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add r0, r0, r8 lsr #16 |
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bl i286a_memoryread |
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ldrh r1, [r9, $r1] |
| |
ldrh r2, [r9, $r2] |
| |
tst r0, #&80 |
| |
orrne r0, r0, #&ff00 |
| |
add r0, r0, r1 |
| |
add r0, r0, r2 |
| |
bic r0, r0, #(3 << 16) |
| |
add r8, r8, #(1 << 16) |
| |
mov pc, r4 |
| |
MEND |
| |
|
| |
MACRO |
| |
$label LER2D16 $r1, $r2 |
| |
$label ldr r0, [r9, #CPU_CS_BASE] |
| |
mov r4, lr |
| |
add r0, r0, r8 lsr #16 |
| |
bl i286a_memoryread_w |
| |
ldrh r1, [r9, $r1] |
| |
ldrh r2, [r9, $r2] |
| |
add r8, r8, #(2 << 16) |
| |
add r12, r1, r0 |
| |
add r12, r12, r2 |
| |
bic r0, r12, #(3 << 16) |
| |
mov pc, r4 |
| |
MEND |
| |
|
| i286a_lea and r1, r0, #(&18 << 3) |
i286a_lea and r1, r0, #(&18 << 3) |
| and r2, r0, #7 |
and r2, r0, #7 |
| add r3, pc, r1 lsr #1 |
add r3, pc, r1 lsr #1 |
|
Line 358 i286a_lea and r1, r0, #(&18 << 3)
|
Line 279 i286a_lea and r1, r0, #(&18 << 3)
|
| b lea_bp_d16 |
b lea_bp_d16 |
| b lea_bx_d16 |
b lea_bx_d16 |
| |
|
| lea_bx_si ldrh r0, [r9, #CPU_BX] |
lea_bx_si LER2 #CPU_BX, #CPU_SI |
| ldrh r1, [r9, #CPU_SI] |
lea_bx_si_d8 LER2D8 #CPU_BX, #CPU_SI |
| add r2, r0, r1 |
lea_bx_si_d16 LER2D16 #CPU_BX, #CPU_SI |
| bic r0, r2, #&10000 |
lea_bx_di LER2 #CPU_BX, #CPU_DI |
| mov pc, lr |
lea_bx_di_d8 LER2D8 #CPU_BX, #CPU_DI |
| |
lea_bx_di_d16 LER2D16 #CPU_BX, #CPU_DI |
| lea_bx_si_d8 mov r4, lr |
lea_bp_si LER2 #CPU_BP, #CPU_SI |
| ldr r0, [r9, #CPU_CS_BASE] |
lea_bp_si_d8 LER2D8 #CPU_BP, #CPU_SI |
| add r0, r0, r8 lsr #16 |
lea_bp_si_d16 LER2D16 #CPU_BP, #CPU_SI |
| bl i286_memoryread |
lea_bp_di LER2 #CPU_BP, #CPU_DI |
| ldrh r1, [r9, #CPU_BX] |
lea_bp_di_d8 LER2D8 #CPU_BP, #CPU_DI |
| ldrh r2, [r9, #CPU_SI] |
lea_bp_di_d16 LER2D16 #CPU_BP, #CPU_DI |
| tst r0, #&80 |
lea_si LER1 #CPU_SI |
| orrne r0, r0, #&ff00 |
lea_si_d8 LER1D8 #CPU_SI |
| add r1, r2, r1 |
lea_si_d16 LER1D16 #CPU_SI |
| add r8, r8, #(1 << 16) |
lea_di LER1 #CPU_DI |
| add r2, r0, r1 |
lea_di_d8 LER1D8 #CPU_DI |
| bic r0, r2, #(3 << 16) |
lea_di_d16 LER1D16 #CPU_DI |
| mov pc, r4 |
lea_bx LER1 #CPU_BX |
| |
lea_bx_d8 LER1D8 #CPU_BX |
| lea_bx_si_d16 mov r4, lr |
lea_bx_d16 LER1D16 #CPU_BX |
| ldr r0, [r9, #CPU_CS_BASE] |
lea_bp_d8 LER1D8 #CPU_BP |
| add r0, r0, r8 lsr #16 |
lea_bp_d16 LER1D16 #CPU_BP |
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldrh r2, [r9, #CPU_SI] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bx_di ldrh r0, [r9, #CPU_BX] |
|
| ldrh r1, [r9, #CPU_DI] |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, lr |
|
| |
|
| lea_bx_di_d8 mov r4, lr |
lea_d16 ldr r0, [r9, #CPU_CS_BASE] |
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
add r0, r0, r8 lsr #16 |
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r1, r2, r1 |
|
| add r8, r8, #(1 << 16) |
|
| add r2, r0, r1 |
|
| bic r0, r2, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bx_di_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
add r8, r8, #(2 << 16) |
| bic r0, r1, #(3 << 16) |
b i286a_memoryread_w |
| mov pc, r4 |
|
| |
|
| lea_bp_si ldrh r0, [r9, #CPU_BP] |
|
| ldrh r1, [r9, #CPU_SI] |
|
| add r2, r0, r1 |
|
| bic r0, r2, #&10000 |
|
| mov pc, lr |
|
| |
|
| lea_bp_si_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_SI] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r1, r2, r1 |
|
| add r8, r8, #(1 << 16) |
|
| add r2, r0, r1 |
|
| bic r0, r2, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bp_si_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_SI] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bp_di ldrh r0, [r9, #CPU_BP] |
|
| ldrh r1, [r9, #CPU_DI] |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, lr |
|
| |
|
| lea_bp_di_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r1, r2, r1 |
|
| add r8, r8, #(1 << 16) |
|
| add r2, r0, r1 |
|
| bic r0, r2, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bp_di_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_si ldrh r0, [r9, #CPU_SI] |
|
| mov pc, lr |
|
| |
|
| lea_si_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_SI] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_si_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_SI] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_di ldrh r0, [r9, #CPU_DI] |
|
| mov pc, lr |
|
| |
|
| lea_di_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_DI] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_di_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_DI] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bx ldrh r0, [r9, #CPU_BX] |
|
| mov pc, lr |
|
| |
|
| lea_bx_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bx_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BX] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| add r8, r8, #(2 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bp_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BP] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| lea_bp_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BP] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| |
|
| ; ---- calc_a |
; ---- calc_a |
| |
|
| |
MACRO |
| |
$label AR1 $r, $b |
| |
$label ldrh r0, [r9, $r] |
| |
ldr r6, [r9, $b] |
| |
mov pc, lr |
| |
MEND |
| |
|
| |
MACRO |
| |
$label AR1D8 $r, $b |
| |
$label ldr r0, [r9, #CPU_CS_BASE] |
| |
mov r4, lr |
| |
add r0, r0, r8 lsr #16 |
| |
bl i286a_memoryread |
| |
ldrh r1, [r9, $r] |
| |
ldr r6, [r9, $b] |
| |
add r8, r8, #(1 << 16) |
| |
tst r0, #&80 |
| |
orrne r0, r0, #&ff00 |
| |
add r0, r0, r1 |
| |
bic r0, r0, #(1 << 16) |
| |
mov pc, r4 |
| |
MEND |
| |
|
| |
MACRO |
| |
$label AR1D16 $r, $b |
| |
$label ldr r0, [r9, #CPU_CS_BASE] |
| |
mov r4, lr |
| |
add r0, r0, r8 lsr #16 |
| |
bl i286a_memoryread_w |
| |
ldrh r1, [r9, $r] |
| |
ldr r6, [r9, $b] |
| |
add r8, r8, #(2 << 16) |
| |
add r3, r1, r0 |
| |
bic r0, r3, #(1 << 16) |
| |
mov pc, r4 |
| |
MEND |
| |
|
| |
MACRO |
| |
$label AR2 $r1, $r2, $b |
| |
$label ldrh r1, [r9, $r1] |
| |
ldrh r2, [r9, $r2] |
| |
ldr r6, [r9, $b] |
| |
add r12, r2, r1 |
| |
bic r0, r12, #(1 << 16) |
| |
mov pc, lr |
| |
MEND |
| |
|
| |
MACRO |
| |
$label AR2D8 $r1, $r2, $b |
| |
$label ldr r0, [r9, #CPU_CS_BASE] |
| |
mov r4, lr |
| |
add r0, r0, r8 lsr #16 |
| |
bl i286a_memoryread |
| |
ldrh r1, [r9, $r1] |
| |
ldrh r2, [r9, $r2] |
| |
ldr r6, [r9, $b] |
| |
tst r0, #&80 |
| |
orrne r0, r0, #&ff00 |
| |
add r0, r0, r1 |
| |
add r0, r0, r2 |
| |
bic r0, r0, #(3 << 16) |
| |
add r8, r8, #(1 << 16) |
| |
mov pc, r4 |
| |
MEND |
| |
|
| |
MACRO |
| |
$label AR2D16 $r1, $r2, $b |
| |
$label ldr r0, [r9, #CPU_CS_BASE] |
| |
mov r4, lr |
| |
add r0, r0, r8 lsr #16 |
| |
bl i286a_memoryread_w |
| |
ldrh r1, [r9, $r1] |
| |
ldrh r2, [r9, $r2] |
| |
ldr r6, [r9, $b] |
| |
add r8, r8, #(2 << 16) |
| |
add r12, r1, r0 |
| |
add r12, r12, r2 |
| |
bic r0, r12, #(3 << 16) |
| |
mov pc, r4 |
| |
MEND |
| |
|
| i286a_a and r1, r0, #(&18 << 3) |
i286a_a and r1, r0, #(&18 << 3) |
| and r2, r0, #7 |
and r2, r0, #7 |
| add r3, pc, r1 lsr #1 |
add r3, pc, r1 lsr #1 |
|
Line 616 i286a_a and r1, r0, #(&18 << 3)
|
Line 415 i286a_a and r1, r0, #(&18 << 3)
|
| b a_bp_d8 |
b a_bp_d8 |
| b a_bx_d8 |
b a_bx_d8 |
| |
|
| b lea_bx_si_d16 |
b a_bx_si_d16 |
| b lea_bx_di_d16 |
b a_bx_di_d16 |
| b lea_bp_si_d16 |
b a_bp_si_d16 |
| b lea_bp_di_d16 |
b a_bp_di_d16 |
| b lea_si_d16 |
b a_si_d16 |
| b lea_di_d16 |
b a_di_d16 |
| b lea_bp_d16 |
b a_bp_d16 |
| b lea_bx_d16 |
b a_bx_d16 |
| |
|
| a_bx_si ldrh r0, [r9, #CPU_BX] |
a_bx_si AR2 #CPU_BX, #CPU_SI, #CPU_DS_FIX |
| ldrh r1, [r9, #CPU_SI] |
a_bx_si_d8 AR2D8 #CPU_BX, #CPU_SI, #CPU_DS_FIX |
| ldr r6, [r9, #CPU_DS_FIX] |
a_bx_si_d16 AR2D16 #CPU_BX, #CPU_SI, #CPU_DS_FIX |
| add r2, r0, r1 |
a_bx_di AR2 #CPU_BX, #CPU_DI, #CPU_DS_FIX |
| bic r0, r2, #&10000 |
a_bx_di_d8 AR2D8 #CPU_BX, #CPU_DI, #CPU_DS_FIX |
| mov pc, lr |
a_bx_di_d16 AR2D16 #CPU_BX, #CPU_DI, #CPU_DS_FIX |
| |
a_bp_si AR2 #CPU_BP, #CPU_SI, #CPU_SS_FIX |
| a_bx_si_d8 mov r4, lr |
a_bp_si_d8 AR2D8 #CPU_BP, #CPU_SI, #CPU_SS_FIX |
| ldr r0, [r9, #CPU_CS_BASE] |
a_bp_si_d16 AR2D16 #CPU_BP, #CPU_SI, #CPU_SS_FIX |
| add r0, r0, r8 lsr #16 |
a_bp_di AR2 #CPU_BP, #CPU_DI, #CPU_SS_FIX |
| bl i286_memoryread |
a_bp_di_d8 AR2D8 #CPU_BP, #CPU_DI, #CPU_SS_FIX |
| ldrh r1, [r9, #CPU_BX] |
a_bp_di_d16 AR2D16 #CPU_BP, #CPU_DI, #CPU_SS_FIX |
| ldrh r2, [r9, #CPU_SI] |
a_si AR1 #CPU_SI, #CPU_DS_FIX |
| ldr r6, [r9, #CPU_DS_FIX] |
a_si_d8 AR1D8 #CPU_SI, #CPU_DS_FIX |
| tst r0, #&80 |
a_si_d16 AR1D16 #CPU_SI, #CPU_DS_FIX |
| orrne r0, r0, #&ff00 |
a_di AR1 #CPU_DI, #CPU_DS_FIX |
| add r1, r2, r1 |
a_di_d8 AR1D8 #CPU_DI, #CPU_DS_FIX |
| add r8, r8, #(1 << 16) |
a_di_d16 AR1D16 #CPU_DI, #CPU_DS_FIX |
| add r2, r0, r1 |
a_bx AR1 #CPU_BX, #CPU_DS_FIX |
| bic r0, r2, #(3 << 16) |
a_bx_d8 AR1D8 #CPU_BX, #CPU_DS_FIX |
| mov pc, r4 |
a_bx_d16 AR1D16 #CPU_BX, #CPU_DS_FIX |
| |
a_bp_d8 AR1D8 #CPU_BP, #CPU_SS_FIX |
| a_bx_si_d16 mov r4, lr |
a_bp_d16 AR1D16 #CPU_BP, #CPU_SS_FIX |
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldrh r2, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bx_di ldrh r0, [r9, #CPU_BX] |
|
| ldrh r1, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, lr |
|
| |
|
| a_bx_di_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r1, r2, r1 |
|
| add r8, r8, #(1 << 16) |
|
| add r2, r0, r1 |
|
| bic r0, r2, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bx_di_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bp_si ldrh r0, [r9, #CPU_BP] |
|
| ldrh r1, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| add r2, r0, r1 |
|
| bic r0, r2, #&10000 |
|
| mov pc, lr |
|
| |
|
| a_bp_si_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r1, r2, r1 |
|
| add r8, r8, #(1 << 16) |
|
| add r2, r0, r1 |
|
| bic r0, r2, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bp_si_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bp_di ldrh r0, [r9, #CPU_BP] |
|
| ldrh r1, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, lr |
|
| |
|
| a_bp_di_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r1, r2, r1 |
|
| add r8, r8, #(1 << 16) |
|
| add r2, r0, r1 |
|
| bic r0, r2, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bp_di_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldrh r2, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| add r3, r0, r1 |
|
| add r1, r3, r2 |
|
| add r8, r8, #(2 << 16) |
|
| bic r0, r1, #(3 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_si ldrh r0, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| mov pc, lr |
|
| |
|
| a_si_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_si_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_SI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_di ldrh r0, [r9, #CPU_DI] |
a_d16 ldr r0, [r9, #CPU_CS_BASE] |
| ldr r6, [r9, #CPU_DS_FIX] |
|
| mov pc, lr |
|
| |
|
| a_di_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_di_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
add r0, r0, r8 lsr #16 |
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_DI] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
ldr r6, [r9, #CPU_DS_FIX] |
| add r8, r8, #(2 << 16) |
add r8, r8, #(2 << 16) |
| add r2, r1, r0 |
b i286a_memoryread_w |
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bx ldrh r0, [r9, #CPU_BX] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| mov pc, lr |
|
| |
|
| a_bx_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bx_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BX] |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldr r6, [r9, #CPU_DS_FIX] |
|
| add r8, r8, #(2 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bp_d8 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread |
|
| ldrh r1, [r9, #CPU_BP] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| tst r0, #&80 |
|
| orrne r0, r0, #&ff00 |
|
| add r2, r0, r1 |
|
| add r8, r8, #(1 << 16) |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| a_bp_d16 mov r4, lr |
|
| ldr r0, [r9, #CPU_CS_BASE] |
|
| ldr r6, [r9, #CPU_SS_FIX] |
|
| add r0, r0, r8 lsr #16 |
|
| bl i286_memoryread_w |
|
| ldrh r1, [r9, #CPU_BP] |
|
| add r8, r8, #(2 << 16) |
|
| add r2, r1, r0 |
|
| bic r0, r2, #(1 << 16) |
|
| mov pc, r4 |
|
| |
|
| |
|
| |
|
| ; ---- test |
|
| |
|
| IMPORT i286core |
|
| EXPORT i286a_ea_test |
|
| EXPORT i286a_lea_test |
|
| EXPORT i286a_a_test |
|
| |
|
| i286a_ea_test stmdb sp!, {r4, r8, r9, lr} |
|
| ldr r9, iet_i286core |
|
| ldrh r8, [r9, #CPU_IP] |
|
| mov r8, r8 lsl #16 |
|
| bl i286a_ea |
|
| mov r8, r8 lsr #16 |
|
| strh r8, [r9, #CPU_IP] |
|
| ldmia sp!, {r4, r8, r9, pc} |
|
| iet_i286core dcd i286core - CPU_REG |
|
| |
|
| i286a_lea_test stmdb sp!, {r4, r8, r9, lr} |
|
| ldr r9, ilt_i286core |
|
| ldrh r8, [r9, #CPU_IP] |
|
| mov r8, r8 lsl #16 |
|
| bl i286a_lea |
|
| mov r8, r8 lsr #16 |
|
| strh r8, [r9, #CPU_IP] |
|
| ldmia sp!, {r4, r8, r9, pc} |
|
| ilt_i286core dcd i286core - CPU_REG |
|
| |
|
| i286a_a_test stmdb sp!, {r4, r8, r9, lr} |
|
| ldr r9, iat_i286core |
|
| ldrh r8, [r9, #CPU_IP] |
|
| mov r8, r8 lsl #16 |
|
| mov r5, r1 |
|
| bl i286a_a |
|
| str r6, [r5] |
|
| mov r8, r8 lsr #16 |
|
| strh r8, [r9, #CPU_IP] |
|
| ldmia sp!, {r4, r8, r9, pc} |
|
| iat_i286core dcd i286core - CPU_REG |
|
| |
|
| END |
END |
| |
|
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