--- np2/i286a/i286a_ea.s	2003/12/16 04:58:00	1.1
+++ np2/i286a/i286a_ea.s	2003/12/19 09:38:25	1.5
@@ -8,12 +8,12 @@
 
 
 	INCLUDE	i286a.inc
-	IMPORT	i286_memoryread
-	IMPORT	i286_memoryread_w
+	IMPORT	i286a_memoryread
+	IMPORT	i286a_memoryread_w
 
 	EXPORT	i286a_ea
 	EXPORT	i286a_lea
-
+	EXPORT	i286a_a
 
 	AREA	.text, CODE, READONLY
 
@@ -62,7 +62,7 @@ ea_bx_si		ldrh	r1, [r9, #CPU_BX]
 ea_bx_si_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_SI]
 				ldr		r3, [r9, #CPU_DS_FIX]
@@ -77,7 +77,7 @@ ea_bx_si_d8		mov		r4, lr
 ea_bx_si_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_SI]
 				ldr		r3, [r9, #CPU_DS_FIX]
@@ -99,7 +99,7 @@ ea_bx_di		ldrh	r1, [r9, #CPU_BX]
 ea_bx_di_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_DI]
 				ldr		r3, [r9, #CPU_DS_FIX]
@@ -114,7 +114,7 @@ ea_bx_di_d8		mov		r4, lr
 ea_bx_di_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_DI]
 				ldr		r3, [r9, #CPU_DS_FIX]
@@ -136,7 +136,7 @@ ea_bp_si		ldrh	r1, [r9, #CPU_BP]
 ea_bp_si_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_SI]
 				ldr		r3, [r9, #CPU_SS_FIX]
@@ -151,7 +151,7 @@ ea_bp_si_d8		mov		r4, lr
 ea_bp_si_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_SI]
 				ldr		r3, [r9, #CPU_SS_FIX]
@@ -173,7 +173,7 @@ ea_bp_di		ldrh	r1, [r9, #CPU_BP]
 ea_bp_di_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_DI]
 				ldr		r3, [r9, #CPU_SS_FIX]
@@ -188,7 +188,7 @@ ea_bp_di_d8		mov		r4, lr
 ea_bp_di_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_DI]
 				ldr		r3, [r9, #CPU_SS_FIX]
@@ -207,7 +207,7 @@ ea_si			ldrh	r1, [r9, #CPU_SI]
 ea_si_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_SI]
 				ldr		r2, [r9, #CPU_DS_FIX]
 				mov		r3, r0 lsl #24
@@ -220,7 +220,7 @@ ea_si_d8		mov		r4, lr
 ea_si_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_SI]
 				ldr		r2, [r9, #CPU_DS_FIX]
 				add		r8, r8, #(2 << 16)
@@ -237,7 +237,7 @@ ea_di			ldrh	r1, [r9, #CPU_DI]
 ea_di_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_DI]
 				ldr		r2, [r9, #CPU_DS_FIX]
 				mov		r3, r0 lsl #24
@@ -250,7 +250,7 @@ ea_di_d8		mov		r4, lr
 ea_di_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_DI]
 				ldr		r2, [r9, #CPU_DS_FIX]
 				add		r8, r8, #(2 << 16)
@@ -267,7 +267,7 @@ ea_bx			ldrh	r1, [r9, #CPU_BX]
 ea_bx_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BX]
 				ldr		r2, [r9, #CPU_DS_FIX]
 				mov		r3, r0 lsl #24
@@ -280,7 +280,7 @@ ea_bx_d8		mov		r4, lr
 ea_bx_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BX]
 				ldr		r2, [r9, #CPU_DS_FIX]
 				add		r8, r8, #(2 << 16)
@@ -292,7 +292,7 @@ ea_bx_d16		mov		r4, lr
 ea_d16			mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldr		r1, [r9, #CPU_DS_FIX]
 				add		r8, r8, #(2 << 16)
 				add		r0, r0, r1
@@ -301,7 +301,7 @@ ea_d16			mov		r4, lr
 ea_bp_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BP]
 				ldr		r2, [r9, #CPU_SS_FIX]
 				mov		r3, r0 lsl #24
@@ -314,7 +314,7 @@ ea_bp_d8		mov		r4, lr
 ea_bp_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BP]
 				ldr		r2, [r9, #CPU_SS_FIX]
 				add		r8, r8, #(2 << 16)
@@ -367,7 +367,7 @@ lea_bx_si		ldrh	r0, [r9, #CPU_BX]
 lea_bx_si_d8	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_SI]
 				tst		r0, #&80
@@ -381,7 +381,7 @@ lea_bx_si_d8	mov		r4, lr
 lea_bx_si_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_SI]
 				add		r3, r0, r1
@@ -399,7 +399,7 @@ lea_bx_di		ldrh	r0, [r9, #CPU_BX]
 lea_bx_di_d8	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_DI]
 				tst		r0, #&80
@@ -413,7 +413,7 @@ lea_bx_di_d8	mov		r4, lr
 lea_bx_di_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BX]
 				ldrh	r2, [r9, #CPU_DI]
 				add		r3, r0, r1
@@ -431,7 +431,7 @@ lea_bp_si		ldrh	r0, [r9, #CPU_BP]
 lea_bp_si_d8	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_SI]
 				tst		r0, #&80
@@ -445,7 +445,7 @@ lea_bp_si_d8	mov		r4, lr
 lea_bp_si_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_SI]
 				add		r3, r0, r1
@@ -463,7 +463,7 @@ lea_bp_di		ldrh	r0, [r9, #CPU_BP]
 lea_bp_di_d8	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_DI]
 				tst		r0, #&80
@@ -477,7 +477,7 @@ lea_bp_di_d8	mov		r4, lr
 lea_bp_di_d16	mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BP]
 				ldrh	r2, [r9, #CPU_DI]
 				add		r3, r0, r1
@@ -492,7 +492,7 @@ lea_si			ldrh	r0, [r9, #CPU_SI]
 lea_si_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_SI]
 				tst		r0, #&80
 				orrne	r0, r0, #&ff00
@@ -504,7 +504,7 @@ lea_si_d8		mov		r4, lr
 lea_si_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_SI]
 				add		r8, r8, #(2 << 16)
 				add		r2, r1, r0
@@ -517,7 +517,7 @@ lea_di			ldrh	r0, [r9, #CPU_DI]
 lea_di_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_DI]
 				tst		r0, #&80
 				orrne	r0, r0, #&ff00
@@ -529,7 +529,7 @@ lea_di_d8		mov		r4, lr
 lea_di_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_DI]
 				add		r8, r8, #(2 << 16)
 				add		r2, r1, r0
@@ -542,7 +542,7 @@ lea_bx			ldrh	r0, [r9, #CPU_BX]
 lea_bx_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BX]
 				tst		r0, #&80
 				orrne	r0, r0, #&ff00
@@ -554,7 +554,7 @@ lea_bx_d8		mov		r4, lr
 lea_bx_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BX]
 				add		r8, r8, #(2 << 16)
 				add		r2, r1, r0
@@ -564,14 +564,14 @@ lea_bx_d16		mov		r4, lr
 lea_d16			mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				add		r8, r8, #(2 << 16)
 				mov		pc, r4
 
 lea_bp_d8		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread
+				bl		i286a_memoryread
 				ldrh	r1, [r9, #CPU_BP]
 				tst		r0, #&80
 				orrne	r0, r0, #&ff00
@@ -583,7 +583,7 @@ lea_bp_d8		mov		r4, lr
 lea_bp_d16		mov		r4, lr
 				ldr		r0, [r9, #CPU_CS_BASE]
 				add		r0, r0, r8 lsr #16
-				bl		i286_memoryread_w
+				bl		i286a_memoryread_w
 				ldrh	r1, [r9, #CPU_BP]
 				add		r8, r8, #(2 << 16)
 				add		r2, r1, r0
@@ -591,6 +591,296 @@ lea_bp_d16		mov		r4, lr
 				mov		pc, r4
 
 
+; ---- calc_a
+
+i286a_a			and		r1, r0, #(&18 << 3)
+				and		r2, r0, #7
+				add		r3, pc, r1 lsr #1
+				add		pc, r3, r2 lsl #2
+
+				b		a_bx_si
+				b		a_bx_di
+				b		a_bp_si
+				b		a_bp_di
+				b		a_si
+				b		a_di
+				b		a_d16
+				b		a_bx
+
+				b		a_bx_si_d8
+				b		a_bx_di_d8
+				b		a_bp_si_d8
+				b		a_bp_di_d8
+				b		a_si_d8
+				b		a_di_d8
+				b		a_bp_d8
+				b		a_bx_d8
+
+				b		a_bx_si_d16
+				b		a_bx_di_d16
+				b		a_bp_si_d16
+				b		a_bp_di_d16
+				b		a_si_d16
+				b		a_di_d16
+				b		a_bp_d16
+				b		a_bx_d16
+
+a_bx_si			ldrh	r0, [r9, #CPU_BX]
+				ldrh	r1, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r2, r0, r1
+				bic		r0, r2, #&10000
+				mov		pc, lr
+
+a_bx_si_d8		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_BX]
+				ldrh	r2, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r1, r2, r1
+				add		r8, r8, #(1 << 16)
+				add		r2, r0, r1
+				bic		r0, r2, #(3 << 16)
+				mov		pc, r4
+
+a_bx_si_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_BX]
+				ldrh	r2, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r3, r0, r1
+				add		r1, r3, r2
+				add		r8, r8, #(2 << 16)
+				bic		r0, r1, #(3 << 16)
+				mov		pc, r4
+
+a_bx_di			ldrh	r0, [r9, #CPU_BX]
+				ldrh	r1, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r2, r1, r0
+				bic		r0, r2, #(1 << 16)
+				mov		pc, lr
+
+a_bx_di_d8		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_BX]
+				ldrh	r2, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r1, r2, r1
+				add		r8, r8, #(1 << 16)
+				add		r2, r0, r1
+				bic		r0, r2, #(3 << 16)
+				mov		pc, r4
+
+a_bx_di_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_BX]
+				ldrh	r2, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r3, r0, r1
+				add		r1, r3, r2
+				add		r8, r8, #(2 << 16)
+				bic		r0, r1, #(3 << 16)
+				mov		pc, r4
+
+a_bp_si			ldrh	r0, [r9, #CPU_BP]
+				ldrh	r1, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				add		r2, r0, r1
+				bic		r0, r2, #&10000
+				mov		pc, lr
+
+a_bp_si_d8		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_BP]
+				ldrh	r2, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r1, r2, r1
+				add		r8, r8, #(1 << 16)
+				add		r2, r0, r1
+				bic		r0, r2, #(3 << 16)
+				mov		pc, r4
+
+a_bp_si_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_BP]
+				ldrh	r2, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				add		r3, r0, r1
+				add		r1, r3, r2
+				add		r8, r8, #(2 << 16)
+				bic		r0, r1, #(3 << 16)
+				mov		pc, r4
+
+a_bp_di			ldrh	r0, [r9, #CPU_BP]
+				ldrh	r1, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				add		r2, r1, r0
+				bic		r0, r2, #(1 << 16)
+				mov		pc, lr
+
+a_bp_di_d8		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_BP]
+				ldrh	r2, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r1, r2, r1
+				add		r8, r8, #(1 << 16)
+				add		r2, r0, r1
+				bic		r0, r2, #(3 << 16)
+				mov		pc, r4
+
+a_bp_di_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_BP]
+				ldrh	r2, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				add		r3, r0, r1
+				add		r1, r3, r2
+				add		r8, r8, #(2 << 16)
+				bic		r0, r1, #(3 << 16)
+				mov		pc, r4
+
+a_si			ldrh	r0, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				mov		pc, lr
+
+a_si_d8			mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r2, r0, r1
+				add		r8, r8, #(1 << 16)
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_si_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_SI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r8, r8, #(2 << 16)
+				add		r2, r1, r0
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_di			ldrh	r0, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				mov		pc, lr
+
+a_di_d8			mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r2, r0, r1
+				add		r8, r8, #(1 << 16)
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_di_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_DI]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r8, r8, #(2 << 16)
+				add		r2, r1, r0
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_bx			ldrh	r0, [r9, #CPU_BX]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				mov		pc, lr
+
+a_bx_d8			mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_BX]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r2, r0, r1
+				add		r8, r8, #(1 << 16)
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_bx_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_BX]
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r8, r8, #(2 << 16)
+				add		r2, r1, r0
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_d16			mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldr		r6, [r9, #CPU_DS_FIX]
+				add		r8, r8, #(2 << 16)
+				mov		pc, r4
+
+a_bp_d8			mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread
+				ldrh	r1, [r9, #CPU_BP]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				tst		r0, #&80
+				orrne	r0, r0, #&ff00
+				add		r2, r0, r1
+				add		r8, r8, #(1 << 16)
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
+a_bp_d16		mov		r4, lr
+				ldr		r0, [r9, #CPU_CS_BASE]
+				ldr		r6, [r9, #CPU_SS_FIX]
+				add		r0, r0, r8 lsr #16
+				bl		i286a_memoryread_w
+				ldrh	r1, [r9, #CPU_BP]
+				add		r8, r8, #(2 << 16)
+				add		r2, r1, r0
+				bic		r0, r2, #(1 << 16)
+				mov		pc, r4
+
 
 
 ; ---- test
@@ -598,6 +888,7 @@ lea_bp_d16		mov		r4, lr
 	IMPORT	i286core
 	EXPORT	i286a_ea_test
 	EXPORT	i286a_lea_test
+	EXPORT	i286a_a_test
 
 i286a_ea_test	stmdb	sp!, {r4, r8, r9, lr}
 				ldr		r9, iet_i286core
@@ -607,7 +898,7 @@ i286a_ea_test	stmdb	sp!, {r4, r8, r9, lr
 				mov		r8, r8 lsr #16
 				strh	r8, [r9, #CPU_IP]
 				ldmia	sp!, {r4, r8, r9, pc}
-iet_i286core	dcd		i286core - CPU_REG
+iet_i286core	dcd		i286core + CPU_SIZE
 
 i286a_lea_test	stmdb	sp!, {r4, r8, r9, lr}
 				ldr		r9, ilt_i286core
@@ -617,7 +908,19 @@ i286a_lea_test	stmdb	sp!, {r4, r8, r9, l
 				mov		r8, r8 lsr #16
 				strh	r8, [r9, #CPU_IP]
 				ldmia	sp!, {r4, r8, r9, pc}
-ilt_i286core	dcd		i286core - CPU_REG
+ilt_i286core	dcd		i286core + CPU_SIZE
+
+i286a_a_test	stmdb	sp!, {r4, r5, r6, r8, r9, lr}
+				ldr		r9, iat_i286core
+				ldrh	r8, [r9, #CPU_IP]
+				mov		r8, r8 lsl #16
+				mov		r5, r1
+				bl		i286a_a
+				str		r6, [r5]
+				mov		r8, r8 lsr #16
+				strh	r8, [r9, #CPU_IP]
+				ldmia	sp!, {r4, r5, r6, r8, r9, pc}
+iat_i286core	dcd		i286core + CPU_SIZE
 
 	END