--- np2/i286a/i286a_i.s	2003/12/19 09:38:25	1.6
+++ np2/i286a/i286a_i.s	2004/01/07 06:53:47	1.10
@@ -1,12 +1,13 @@
 
 	INCLUDE		i286a.inc
 
-	IMPORT		i286core
+	IMPORT		i286acore
 	IMPORT		i286a_memoryread
-	IMPORT		i286_memorywrite_w
+	IMPORT		i286a_memorywrite_w
 	EXPORT		i286a_localint
 	EXPORT		i286a_trapint
 	IMPORT		i286a_trapintr
+	EXPORT		i286c_interrupt
 	EXPORT		i286a_interrupt
 
 	AREA	.text, CODE, READONLY
@@ -19,21 +20,21 @@ i286a_localint	ldrh	r4, [r9, #CPU_SP]
 				sub		r4, r4, #(2 << 16)
 				mov		r1, r8
 				add		r0, r5, r4 lsr #16
-				bl		i286_memorywrite_w
+				bl		i286a_memorywrite_w
 				sub		r4, r4, #(2 << 16)
 				ldrh	r1, [r9, #CPU_CS]
 				add		r0, r5, r4 lsr #16
-				bl		i286_memorywrite_w
+				bl		i286a_memorywrite_w
 				sub		r4, r4, #(2 << 16)
 				mov		r1, r8 lsr #16
 				mov		r4, r4 lsr #16
 				sub		r8, r8, r1 lsl #16
 				add		r0, r4, r5
 				strh	r4, [r9, #CPU_SP]
-				bl		i286_memorywrite_w
-				mov		r0, #0
+				bl		i286a_memorywrite_w
+			;;	mov		r0, #0
 				ldr		r1, [r9, r6 lsl #2]
-				strb	r0, [r9, #CPU_TRAP]
+			;;	strb	r0, [r9, #CPU_TRAP]
 				bic		r8, r8, #(T_FLAG + I_FLAG)
 				mov		r0, r1 lsr #16
 				orr		r8, r8, r1 lsl #16
@@ -49,21 +50,21 @@ i286a_trapint	ldrh	r4, [r9, #CPU_SP]
 				sub		r4, r4, #(2 << 16)
 				mov		r1, r8
 				add		r0, r5, r4 lsr #16
-				bl		i286_memorywrite_w
+				bl		i286a_memorywrite_w
 				sub		r4, r4, #(2 << 16)
 				ldrh	r1, [r9, #CPU_CS]
 				add		r0, r5, r4 lsr #16
-				bl		i286_memorywrite_w
+				bl		i286a_memorywrite_w
 				sub		r4, r4, #(2 << 16)
 				mov		r1, r8 lsr #16
 				mov		r4, r4 lsr #16
 				sub		r8, r8, r1 lsl #16
 				add		r0, r4, r5
 				strh	r4, [r9, #CPU_SP]
-				bl		i286_memorywrite_w
-				mov		r0, #0
+				bl		i286a_memorywrite_w
+			;;	mov		r0, #0
 				ldr		r1, [r9, #4]
-				strb	r0, [r9, #CPU_TRAP]
+			;;	strb	r0, [r9, #CPU_TRAP]
 				bic		r8, r8, #(T_FLAG + I_FLAG)
 				mov		r0, r1 lsr #16
 				orr		r8, r8, r1 lsl #16
@@ -72,7 +73,7 @@ i286a_trapint	ldrh	r4, [r9, #CPU_SP]
 				str		r2, [r9, #CPU_CS_BASE]
 				b		i286a_trapintr
 
-
+i286c_interrupt
 i286a_interrupt	ldr		r1, iai_r9
 				stmdb	sp!, {r4 - r9, lr}
 				mov		r9, r1
@@ -90,30 +91,30 @@ i286a_interrupt	ldr		r1, iai_r9
 				sub		r4, r4, #(2 << 16)
 				mov		r1, r8
 				add		r0, r5, r4 lsr #16
-				bl		i286_memorywrite_w
+				bl		i286a_memorywrite_w
 				sub		r4, r4, #(2 << 16)
 				ldrh	r1, [r9, #CPU_CS]
 				add		r0, r5, r4 lsr #16
-				bl		i286_memorywrite_w
+				bl		i286a_memorywrite_w
 				sub		r4, r4, #(2 << 16)
 				mov		r1, r8 lsr #16
 				mov		r4, r4 lsr #16
 				sub		r8, r8, r1 lsl #16
 				add		r0, r4, r5
 				strh	r4, [r9, #CPU_SP]
-				bl		i286_memorywrite_w
-				mov		r0, #0
+				bl		i286a_memorywrite_w
+			;;	mov		r0, #0
 				ldr		r1, [r9, r6 lsl #2]
-				strb	r0, [r9, #CPU_TRAP]
+			;;	strb	r0, [r9, #CPU_TRAP]
 				bic		r8, r8, #(T_FLAG + I_FLAG)
 				mov		r0, r1 lsr #16
 				orr		r8, r8, r1 lsl #16
 				mov		r2, r0 lsl #4
 				strh	r0, [r9, #CPU_CS]
 				str		r2, [r9, #CPU_CS_BASE]
-				CPUSVC
+				CPUSV
 				ldmia	sp!, {r4 - r9, pc}
-iai_r9			dcd		i286core + CPU_SIZE
+iai_r9			dcd		i286acore + CPU_SIZE
 
 	END