--- np2/i286a/i286a_i.s 2003/12/21 23:27:08 1.8 +++ np2/i286a/i286a_i.s 2004/01/07 12:51:29 1.11 @@ -1,13 +1,13 @@ INCLUDE i286a.inc - IMPORT i286core + IMPORT i286acore IMPORT i286a_memoryread IMPORT i286a_memorywrite_w EXPORT i286a_localint EXPORT i286a_trapint - IMPORT i286a_trapintr - EXPORT i286c_interrupt +;; IMPORT i286a_trapintr +;; EXPORT i286c_interrupt EXPORT i286a_interrupt AREA .text, CODE, READONLY @@ -32,9 +32,9 @@ i286a_localint ldrh r4, [r9, #CPU_SP] add r0, r4, r5 strh r4, [r9, #CPU_SP] bl i286a_memorywrite_w - mov r0, #0 + ;; mov r0, #0 ldr r1, [r9, r6 lsl #2] - strb r0, [r9, #CPU_TRAP] + ;; strb r0, [r9, #CPU_TRAP] bic r8, r8, #(T_FLAG + I_FLAG) mov r0, r1 lsr #16 orr r8, r8, r1 lsl #16 @@ -43,7 +43,8 @@ i286a_localint ldrh r4, [r9, #CPU_SP] str r2, [r9, #CPU_CS_BASE] mov pc, r11 -i286a_trapint ldrh r4, [r9, #CPU_SP] +i286a_trapint mov r6, lr + ldrh r4, [r9, #CPU_SP] ldr r5, [r9, #CPU_SS_BASE] CPUWORK #20 mov r4, r4 lsl #16 @@ -62,18 +63,18 @@ i286a_trapint ldrh r4, [r9, #CPU_SP] add r0, r4, r5 strh r4, [r9, #CPU_SP] bl i286a_memorywrite_w - mov r0, #0 + ;; mov r0, #0 ldr r1, [r9, #4] - strb r0, [r9, #CPU_TRAP] + ;; strb r0, [r9, #CPU_TRAP] bic r8, r8, #(T_FLAG + I_FLAG) mov r0, r1 lsr #16 orr r8, r8, r1 lsl #16 mov r2, r0 lsl #4 strh r0, [r9, #CPU_CS] str r2, [r9, #CPU_CS_BASE] - b i286a_trapintr + mov pc, r6 -i286c_interrupt +;; i286c_interrupt i286a_interrupt ldr r1, iai_r9 stmdb sp!, {r4 - r9, lr} mov r9, r1 @@ -103,9 +104,9 @@ i286a_interrupt ldr r1, iai_r9 add r0, r4, r5 strh r4, [r9, #CPU_SP] bl i286a_memorywrite_w - mov r0, #0 + ;; mov r0, #0 ldr r1, [r9, r6 lsl #2] - strb r0, [r9, #CPU_TRAP] + ;; strb r0, [r9, #CPU_TRAP] bic r8, r8, #(T_FLAG + I_FLAG) mov r0, r1 lsr #16 orr r8, r8, r1 lsl #16 @@ -114,7 +115,7 @@ i286a_interrupt ldr r1, iai_r9 str r2, [r9, #CPU_CS_BASE] CPUSV ldmia sp!, {r4 - r9, pc} -iai_r9 dcd i286core + CPU_SIZE +iai_r9 dcd i286acore + CPU_SIZE END