np2/i286a/i286a_mn.s - diff

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Diff for /np2/i286a/i286a_mn.s between versions 1.16 and 1.23

version 1.16, 2003/12/22 07:41:15	version 1.23, 2004/01/29 00:27:29
Line 9	Line 9
IMPORT iflags	IMPORT iflags
IMPORT i286a_localint	IMPORT i286a_localint
IMPORT i286a_trapint	IMPORT i286a_trapint
EXPORT i286a_trapintr	IMPORT i286a_selector
IMPORT i286a_ea	IMPORT i286a_ea
IMPORT i286a_lea	IMPORT i286a_lea
IMPORT i286a_a	IMPORT i286a_a
Line 665 jmps JMPS #7	Line 665 jmps JMPS #7
xchg_ea_r8 EAREG8 r6	xchg_ea_r8 EAREG8 r6
cmp r0, #&c0	cmp r0, #&c0
bcc xchgear8_1	bcc xchgear8_1
R8SRC r0, r5	R8SRC r0, r2
ldrb r0, [r6, #CPU_REG]	ldrb r0, [r6, #CPU_REG]
ldrb r1, [r5, #CPU_REG]	ldrb r1, [r2, #CPU_REG]
CPUWORK #3	CPUWORK #3
strb r0, [r5, #CPU_REG]	strb r0, [r2, #CPU_REG]
strb r1, [r6, #CPU_REG]	strb r1, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
xchgear8_1 bl i286a_ea	xchgear8_1 bl i286a_ea
Line 693 xchgear8_2 mov r5, r0	Line 693 xchgear8_2 mov r5, r0
xchg_ea_r16 EAREG16 r6	xchg_ea_r16 EAREG16 r6
cmp r0, #&c0	cmp r0, #&c0
bcc xchgear16_1	bcc xchgear16_1
R16SRC r0, r5	R16SRC r0, r2
ldrh r0, [r6, #CPU_REG]	ldrh r0, [r6, #CPU_REG]
ldrh r1, [r5, #CPU_REG]	ldrh r1, [r2, #CPU_REG]
CPUWORK #3	CPUWORK #3
strh r0, [r5, #CPU_REG]	strh r0, [r2, #CPU_REG]
strh r1, [r6, #CPU_REG]	strh r1, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
xchgear16_1 bl i286a_ea	xchgear16_1 bl i286a_ea
tst r0, #1	WORDACC r0, xchgear16_2
bne xchgear16_2
cmp r0, #I286_MEMWRITEMAX
bcs xchgear16_2
ldrh r1, [r6, #CPU_REG]	ldrh r1, [r6, #CPU_REG]
ldrh r4, [r9, r0]	ldrh r4, [r9, r0]
CPUWORK #5	CPUWORK #5
Line 724 mov_ea_r8 EAREG8 r6	Line 721 mov_ea_r8 EAREG8 r6
cmp r0, #&c0	cmp r0, #&c0
bcc movear8_1	bcc movear8_1
ldrb r1, [r6, #CPU_REG]	ldrb r1, [r6, #CPU_REG]
R8SRC r0, r5	R8SRC r0, r2
CPUWORK #3	CPUWORK #3
strb r1, [r5, #CPU_REG]	strb r1, [r2, #CPU_REG]
mov pc, r11	mov pc, r11
movear8_1 CPUWORK #5	movear8_1 CPUWORK #5
bl i286a_ea	bl i286a_ea
Line 738 mov_ea_r16 EAREG16 r6	Line 735 mov_ea_r16 EAREG16 r6
cmp r0, #&c0	cmp r0, #&c0
bcc movear16_1	bcc movear16_1
ldrh r1, [r6, #CPU_REG]	ldrh r1, [r6, #CPU_REG]
R16SRC r0, r5	R16SRC r0, r2
CPUWORK #3	CPUWORK #3
strh r1, [r5, #CPU_REG]	strh r1, [r2, #CPU_REG]
mov pc, r11	mov pc, r11
movear16_1 CPUWORK #5	movear16_1 CPUWORK #5
bl i286a_ea	bl i286a_ea
Line 784 leareg mov r6, #6	Line 781 leareg mov r6, #6
sub r8, r8, #(2 << 16)	sub r8, r8, #(2 << 16)
b i286a_localint	b i286a_localint

mov_seg_ea GETPCF8	mov_seg_ea ldrh r6, [r9, #CPU_MSW]
adr r6, msegea_tbl	GETPCF8
	adr r2, msegea_tbl
and r1, r0, #(3 << 3)	and r1, r0, #(3 << 3)
mov r5, r8	tst r6, #MSW_PE
ldr r6, [r6, r1 lsr #1]	orrne r1, r1, #(4 << 3)
	mov r6, r8
	ldr r2, [r2, r1 lsr #1]
cmp r0, #&c0	cmp r0, #&c0
bcc msegeam	bcc msegeam
CPUWORK #2
R16SRC r0, r4	R16SRC r0, r4
	CPUWORK #2
ldrh r0, [r4, #CPU_REG]	ldrh r0, [r4, #CPU_REG]
mov pc, r6	mov pc, r2
msegeam CPUWORK #5	msegeam str r2, [sp, #-4]!
	CPUWORK #5
bl i286a_ea	bl i286a_ea
bl i286a_memoryread_w	ldr lr, [sp], #4
mov pc, r6	b i286a_memoryread_w
msegea_tbl dcd msegea_es	msegea_tbl dcd msegea_es
dcd msegea_cs	dcd msegea_cs
dcd msegea_ss	dcd msegea_ss
dcd msegea_ds	dcd msegea_ds
	dcd msegea_es_p
	dcd msegea_cs
	dcd msegea_ss_p
	dcd msegea_ds_p
msegea_es mov r1, r0 lsl #4	msegea_es mov r1, r0 lsl #4
strh r0, [r9, #CPU_ES]	strh r0, [r9, #CPU_ES]
str r1, [r9, #CPU_ES_BASE]	str r1, [r9, #CPU_ES_BASE]
Line 817 msegea_ss mov r1, r0 lsl #4	Line 822 msegea_ss mov r1, r0 lsl #4
str r1, [r9, #CPU_SS_BASE]	str r1, [r9, #CPU_SS_BASE]
str r1, [r9, #CPU_SS_FIX]	str r1, [r9, #CPU_SS_FIX]
NEXT_OPCODE	NEXT_OPCODE
msegea_cs sub r8, r5, #(2 << 16)
	msegea_es_p strh r0, [r9, #CPU_ES]
	bl i286a_selector
	str r0, [r9, #CPU_ES_BASE]
	mov pc, r11
	msegea_ds_p strh r0, [r9, #CPU_DS]
	bl i286a_selector
	str r0, [r9, #CPU_DS_BASE]
	str r0, [r9, #CPU_DS_FIX]
	mov pc, r11
	msegea_ss_p strh r0, [r9, #CPU_SS]
	bl i286a_selector
	str r0, [r9, #CPU_SS_BASE]
	str r0, [r9, #CPU_SS_FIX]
	NEXT_OPCODE

	msegea_cs sub r8, r6, #(2 << 16)
mov r6, #6	mov r6, #6
b i286a_localint	b i286a_localint


pop_ea POP #5	pop_ea POP #5
mov r6, r0	mov r6, r0
GETPCF8	GETPCF8
Line 920 pushf CPUWORK #3	Line 942 pushf CPUWORK #3
b i286a_memorywrite_w	b i286a_memorywrite_w

popf POP #5	popf POP #5
	if 1
	mov r8, r8 lsr #16
	bic r1, r0, #&f000 ; i286
	and r2, r0, #(I_FLAG + T_FLAG)
	orr r8, r1, r8 lsl #16
	cmp r2, #(I_FLAG + T_FLAG)
	beq popf_withirq
	else
mov r2, #3	mov r2, #3
mov r8, r8 lsr #16	mov r8, r8 lsr #16
and r2, r2, r0 lsr #8	and r2, r2, r0 lsr #8
Line 928 popf POP #5	Line 958 popf POP #5
orr r8, r1, r8 lsl #16	orr r8, r1, r8 lsl #16
strb r2, [r9, #CPU_TRAP]	strb r2, [r9, #CPU_TRAP]
bne popf_withirq	bne popf_withirq
	endif
ldr r0, popf_pic	ldr r0, popf_pic
NOINTREXIT	NOINTREXIT
popf_withirq I286IRQCHECKTERM	popf_withirq I286IRQCHECKTERM
Line 977 mov_m16_ax CPUWORK #5	Line 1008 mov_m16_ax CPUWORK #5
b i286a_memorywrite_w	b i286a_memorywrite_w

movsb CPUWORK #5	movsb CPUWORK #5
ldrh r5, [r9, #CPU_SI]	ldrh r6, [r9, #CPU_SI]
ldr r0, [r9, #CPU_DS_FIX]	ldr r0, [r9, #CPU_DS_FIX]
tst r8, #D_FLAG	tst r8, #D_FLAG
moveq r4, #1	moveq r4, #1
movne r4, #-1	movne r4, #-1
add r0, r5, r0	add r0, r6, r0
bl i286a_memoryread	bl i286a_memoryread
ldrh r3, [r9, #CPU_DI]	ldrh r3, [r9, #CPU_DI]
ldr r2, [r9, #CPU_ES_BASE]	ldr r2, [r9, #CPU_ES_BASE]
add r5, r5, r4	add r6, r6, r4
mov r1, r0	mov r1, r0
add r0, r3, r2	add r0, r3, r2
add r3, r3, r4	add r3, r3, r4
strh r5, [r9, #CPU_SI]	strh r6, [r9, #CPU_SI]
strh r3, [r9, #CPU_DI]	strh r3, [r9, #CPU_DI]
mov lr, r11	mov lr, r11
b i286a_memorywrite	b i286a_memorywrite

movsw CPUWORK #5	movsw CPUWORK #5
ldrh r5, [r9, #CPU_SI]	ldrh r6, [r9, #CPU_SI]
ldr r0, [r9, #CPU_DS_FIX]	ldr r0, [r9, #CPU_DS_FIX]
tst r8, #D_FLAG	tst r8, #D_FLAG
moveq r4, #2	moveq r4, #2
movne r4, #-2	movne r4, #-2
add r0, r5, r0	add r0, r6, r0
bl i286a_memoryread_w	bl i286a_memoryread_w
ldrh r3, [r9, #CPU_DI]	ldrh r3, [r9, #CPU_DI]
ldr r2, [r9, #CPU_ES_BASE]	ldr r2, [r9, #CPU_ES_BASE]
add r5, r5, r4	add r6, r6, r4
mov r1, r0	mov r1, r0
add r0, r3, r2	add r0, r3, r2
add r3, r3, r4	add r3, r3, r4
strh r5, [r9, #CPU_SI]	strh r6, [r9, #CPU_SI]
strh r3, [r9, #CPU_DI]	strh r3, [r9, #CPU_DI]
mov lr, r11	mov lr, r11
b i286a_memorywrite_w	b i286a_memorywrite_w
Line 1354 into CPUWORK #4	Line 1385 into CPUWORK #4
mov r6, #4	mov r6, #4
b i286a_localint	b i286a_localint

iret bl extirq_pop	iret ldrh r1, [r9, #CPU_SP]
ldrh r1, [r9, #CPU_SP]
ldr r5, [r9, #CPU_SS_BASE]	ldr r5, [r9, #CPU_SS_BASE]
CPUWORK #31	CPUWORK #31
add r4, r1, #2	add r4, r1, #2
Line 1374 iret bl extirq_pop	Line 1404 iret bl extirq_pop
add r4, r4, #2	add r4, r4, #2
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
	if 1
	bic r1, r0, #&f000
	and r2, r0, #(I_FLAG + T_FLAG)
	orr r8, r1, r8
	cmp r2, #(I_FLAG + T_FLAG)
	beq iret_withirq
	else
mov r2, #3	mov r2, #3
bic r1, r0, #&f000 ; i286	bic r1, r0, #&f000 ; i286
and r2, r2, r0 lsr #8	and r2, r2, r0 lsr #8
Line 1381 iret bl extirq_pop	Line 1418 iret bl extirq_pop
ands r2, r2, r2 lsr #1	ands r2, r2, r2 lsr #1
strb r2, [r9, #CPU_TRAP]	strb r2, [r9, #CPU_TRAP]
bne iret_withirq	bne iret_withirq
	endif
ldr r0, iret_pic	ldr r0, iret_pic
NOINTREXIT	NOINTREXIT
iret_withirq I286IRQCHECKTERM	iret_withirq I286IRQCHECKTERM
Line 1498 jcxz ldrh r0, [r9, #CPU_CX]	Line 1536 jcxz ldrh r0, [r9, #CPU_CX]
mov pc, r11	mov pc, r11
jcxzj JMPS #8	jcxzj JMPS #8

in_al_d8 CPUWORK #5	in_al_d8 GETPCF8
GETPCF8	CPUWORK #5
add r3, r0, r8 lsr #16	add r3, r5, r8 lsr #16
CPUSV	CPUSV
str r3, [r9, #CPU_INPUT]	str r3, [r9, #CPU_INPUT]
bl iocore_inp8	bl iocore_inp8
Line 1623 stc CPUWORK #2	Line 1661 stc CPUWORK #2
mov pc, r11	mov pc, r11

cli CPUWORK #2	cli CPUWORK #2
	if 1
	bic r8, r8, #I_FLAG
	else
mov r0, #0	mov r0, #0
bic r8, r8, #I_FLAG	bic r8, r8, #I_FLAG
strb r0, [r9, #CPU_TRAP]	strb r0, [r9, #CPU_TRAP]
	endif
mov pc, r11	mov pc, r11

sti CPUWORK #2	sti CPUWORK #2
tst r8, #I_FLAG	tst r8, #I_FLAG
bne sti_noirq	bne sti_noirq
sti_set orr r8, r8, #I_FLAG	sti_set orr r8, r8, #I_FLAG
	if 1
	ldr r0, sti_pic
	tst r8, #T_FLAG
	bne sti_withirq
	else
mov r1, #(T_FLAG >> 8)	mov r1, #(T_FLAG >> 8)
ands r1, r1, r8 lsr #8	ands r1, r1, r8 lsr #8
ldr r0, sti_pic	ldr r0, sti_pic
strneb r1, [r9, #CPU_TRAP]	strneb r1, [r9, #CPU_TRAP]
bne sti_withirq	bne sti_withirq
PICEXISTINTR sti_noirq	endif
	PICEXISTINTR
bne sti_withirq	bne sti_withirq
sti_noirq NEXT_OPCODE	sti_noirq NEXT_OPCODE
sti_pic dcd pic	sti_pic dcd pic
Line 1680 i286a stmdb sp!, {r4 - r11, lr}	Line 1728 i286a stmdb sp!, {r4 - r11, lr}
ldr r10, ias_r10	ldr r10, ias_r10
CPULD	CPULD
ldr r5, [r9, #CPU_CS_BASE]	ldr r5, [r9, #CPU_CS_BASE]
ldr r1, [r2, #DMAC_WORKING]	ldrb r1, [r2, #DMAC_WORKING]
and r0, r8, #(I_FLAG + T_FLAG)	and r0, r8, #(I_FLAG + T_FLAG)
cmp r0, #(I_FLAG + T_FLAG)	cmp r0, #(I_FLAG + T_FLAG)
beq i286awithtrap	beq i286awithtrap
Line 1729 i286awithtrap adr r4, optbl1	Line 1777 i286awithtrap adr r4, optbl1
bl dmap_i286	bl dmap_i286
and r0, r8, #(I_FLAG + T_FLAG)	and r0, r8, #(I_FLAG + T_FLAG)
cmp r0, #(I_FLAG + T_FLAG)	cmp r0, #(I_FLAG + T_FLAG)
beq i286a_trapint	bleq i286a_trapint
i286a_trapintr CPUSV	CPUSV
ldmia sp!, {r4 - r11, pc}	ldmia sp!, {r4 - r11, pc}

optbl1 dcd add_ea_r8 ; 00	optbl1 dcd add_ea_r8 ; 00
Line 1941 optbl1 dcd add_ea_r8 ; 00	Line 1989 optbl1 dcd add_ea_r8 ; 00
dcd i286asft16_d8	dcd i286asft16_d8
dcd ret_near_d16	dcd ret_near_d16
dcd ret_near	dcd ret_near
dcd les_r16_ea ; (now testing i286a_a)	dcd les_r16_ea
dcd lds_r16_ea ; (now testing i286a_a)	dcd lds_r16_ea
dcd mov_ea8_d8	dcd mov_ea8_d8
dcd mov_ea16_d16	dcd mov_ea16_d16
dcd enter	dcd enter

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Removed from v.1.16
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	Added in v.1.23