np2/i286a/i286a_mn.s - diff

Return to i286a_mn.s CVS log

Up to [RetroPC.NET] / np2 / i286a

Diff for /np2/i286a/i286a_mn.s between versions 1.20 and 1.29

version 1.20, 2004/01/05 15:47:18	version 1.29, 2005/05/16 04:55:13
Line 9	Line 9
IMPORT iflags	IMPORT iflags
IMPORT i286a_localint	IMPORT i286a_localint
IMPORT i286a_trapint	IMPORT i286a_trapint
EXPORT i286a_trapintr	IMPORT i286a_selector
IMPORT i286a_ea	IMPORT i286a_ea
IMPORT i286a_lea	IMPORT i286a_lea
IMPORT i286a_a	IMPORT i286a_a
Line 24	Line 24
IMPORT iocore_out8	IMPORT iocore_out8
IMPORT iocore_out16	IMPORT iocore_out16

IMPORT dmap_i286	IMPORT dmax86
IMPORT biosfunc	IMPORT biosfunc

IMPORT i286a_cts	IMPORT i286a_cts
Line 96 adc_r16_ea OP_R16_EA ADC16, #2, #7	Line 96 adc_r16_ea OP_R16_EA ADC16, #2, #7
adc_al_d8 OP_AL_D8 ADC8, #3	adc_al_d8 OP_AL_D8 ADC8, #3
adc_ax_d16 OP_AX_D16 ADC16, #3	adc_ax_d16 OP_AX_D16 ADC16, #3
push_ss REGPUSH #CPU_SS, #3	push_ss REGPUSH #CPU_SS, #3
pop_ss SEGPOPFIX #CPU_SS, #CPU_SS_BASE, #CPU_SS_FIX, #5	; pop_ss

sbb_ea_r8 OP_EA_R8 SBB8, #2, #7	sbb_ea_r8 OP_EA_R8 SBB8, #2, #7
sbb_ea_r16 OP_EA_R16 SBB16, #2, #7	sbb_ea_r16 OP_EA_R16 SBB16, #2, #7
Line 105 sbb_r16_ea OP_R16_EA SBB16, #2, #7	Line 105 sbb_r16_ea OP_R16_EA SBB16, #2, #7
sbb_al_d8 OP_AL_D8 SBB8, #3	sbb_al_d8 OP_AL_D8 SBB8, #3
sbb_ax_d16 OP_AX_D16 SBB16, #3	sbb_ax_d16 OP_AX_D16 SBB16, #3
push_ds REGPUSH #CPU_DS, #3	push_ds REGPUSH #CPU_DS, #3
pop_ds SEGPOPFIX #CPU_DS, #CPU_DS_BASE, #CPU_DS_FIX, #5	; pop_ds SEGPOPFIX #CPU_DS, #CPU_DS_BASE, #CPU_DS_FIX, #5

and_ea_r8 OP_EA_R8 AND8, #2, #7	and_ea_r8 OP_EA_R8 AND8, #2, #7
and_ea_r16 OP_EA_R16 AND16, #2, #7	and_ea_r16 OP_EA_R16 AND16, #2, #7
Line 134 xor_ax_d16 OP_AX_D16 XOR16, #3	Line 134 xor_ax_d16 OP_AX_D16 XOR16, #3
; segprefix_ss !	; segprefix_ss !
; aaa *	; aaa *

cmp_ea_r8 S_EA_R8 SUB8, #2, #7	cmp_ea_r8 S_EA_R8 SUB8, #2, #6
cmp_ea_r16 S_EA_R16 SUB16, #2, #7	cmp_ea_r16 S_EA_R16 SUB16, #2, #6
cmp_r8_ea S_R8_EA SUB8, #2, #6	cmp_r8_ea S_R8_EA SUB8, #2, #6
cmp_r16_ea S_R16_EA SUB16, #2, #6	cmp_r16_ea S_R16_EA SUB16, #2, #6
cmp_al_d8 S_AL_D8 SUB8, #3	cmp_al_d8 S_AL_D8 SUB8, #3
Line 190 pop_di REGPOP #CPU_DI, #5	Line 190 pop_di REGPOP #CPU_DI, #5
; outsb *	; outsb *
; outsw *	; outsw *

jo_short JMPNE #O_FLAG, #2, #7	jo_short JMPNE #O_FLAG, #3, #7
jno_short JMPEQ #O_FLAG, #2, #7	jno_short JMPEQ #O_FLAG, #3, #7
jc_short JMPNE #C_FLAG, #2, #7	jc_short JMPNE #C_FLAG, #3, #7
jnc_short JMPEQ #C_FLAG, #2, #7	jnc_short JMPEQ #C_FLAG, #3, #7
jz_short JMPNE #Z_FLAG, #2, #7	jz_short JMPNE #Z_FLAG, #3, #7
jnz_short JMPEQ #Z_FLAG, #2, #7	jnz_short JMPEQ #Z_FLAG, #3, #7
jna_short JMPNE #(Z_FLAG + C_FLAG), #2, #7	jna_short JMPNE #(Z_FLAG + C_FLAG), #3, #7
ja_short JMPEQ #(Z_FLAG + C_FLAG), #2, #7	ja_short JMPEQ #(Z_FLAG + C_FLAG), #3, #7
js_short JMPNE #S_FLAG, #2, #7	js_short JMPNE #S_FLAG, #3, #7
jns_short JMPEQ #S_FLAG, #2, #7	jns_short JMPEQ #S_FLAG, #3, #7
jp_short JMPNE #P_FLAG, #2, #7	jp_short JMPNE #P_FLAG, #3, #7
jnp_short JMPEQ #P_FLAG, #2, #7	jnp_short JMPEQ #P_FLAG, #3, #7
; jl_short +	; jl_short +
; jnl_short +	; jnl_short +
; jle_short +	; jle_short +
Line 341 reserved mov r6, #6	Line 341 reserved mov r6, #6
sub r8, r8, #(1 << 16)	sub r8, r8, #(1 << 16)
b i286a_localint	b i286a_localint

	pop_ss SEGPOPFIX #CPU_SS, #CPU_SS_BASE, #CPU_SS_FIX, #5
	NEXT_OPCODE

	pop_ds SEGPOPFIX #CPU_DS, #CPU_DS_BASE, #CPU_DS_FIX, #5
	mov pc, r11

daa ldrb r0, [r9, #CPU_AL]	daa ldrb r0, [r9, #CPU_AL]
bic r8, r8, #O_FLAG	bic r8, r8, #O_FLAG
CPUWORK #3	CPUWORK #3
Line 650 jle_short tst r8, #Z_FLAG	Line 656 jle_short tst r8, #Z_FLAG
jl_short eor r0, r8, r8 lsr #4	jl_short eor r0, r8, r8 lsr #4
tst r0, #S_FLAG	tst r0, #S_FLAG
bne jmps	bne jmps
nojmps CPUWORK #2	nojmps CPUWORK #3
add r8, r8, #(1 << 16)	add r8, r8, #(1 << 16)
mov pc, r11	mov pc, r11

Line 701 xchg_ea_r16 EAREG16 r6	Line 707 xchg_ea_r16 EAREG16 r6
strh r1, [r6, #CPU_REG]	strh r1, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
xchgear16_1 bl i286a_ea	xchgear16_1 bl i286a_ea
WORDACC r0, xchgear16_2	ACCWORD r0, xchgear16_2
ldrh r1, [r6, #CPU_REG]	ldrh r1, [r6, #CPU_REG]
ldrh r4, [r9, r0]	ldrh r4, [r9, r0]
CPUWORK #5	CPUWORK #5
Line 781 leareg mov r6, #6	Line 787 leareg mov r6, #6
sub r8, r8, #(2 << 16)	sub r8, r8, #(2 << 16)
b i286a_localint	b i286a_localint

mov_seg_ea GETPCF8	mov_seg_ea ldrb r6, [r9, #CPU_MSW]
	GETPCF8
adr r2, msegea_tbl	adr r2, msegea_tbl
and r1, r0, #(3 << 3)	and r1, r0, #(3 << 3)
	tst r6, #MSW_PE
	orrne r1, r1, #(4 << 3)
mov r6, r8	mov r6, r8
ldr r2, [r2, r1 lsr #1]	ldr r2, [r2, r1 lsr #1]
cmp r0, #&c0	cmp r0, #&c0
Line 801 msegea_tbl dcd msegea_es	Line 810 msegea_tbl dcd msegea_es
dcd msegea_cs	dcd msegea_cs
dcd msegea_ss	dcd msegea_ss
dcd msegea_ds	dcd msegea_ds
	dcd msegea_es_p
	dcd msegea_cs
	dcd msegea_ss_p
	dcd msegea_ds_p
msegea_es mov r1, r0 lsl #4	msegea_es mov r1, r0 lsl #4
strh r0, [r9, #CPU_ES]	strh r0, [r9, #CPU_ES]
str r1, [r9, #CPU_ES_BASE]	str r1, [r9, #CPU_ES_BASE]
Line 815 msegea_ss mov r1, r0 lsl #4	Line 828 msegea_ss mov r1, r0 lsl #4
str r1, [r9, #CPU_SS_BASE]	str r1, [r9, #CPU_SS_BASE]
str r1, [r9, #CPU_SS_FIX]	str r1, [r9, #CPU_SS_FIX]
NEXT_OPCODE	NEXT_OPCODE

	msegea_es_p strh r0, [r9, #CPU_ES]
	bl i286a_selector
	str r0, [r9, #CPU_ES_BASE]
	mov pc, r11
	msegea_ds_p strh r0, [r9, #CPU_DS]
	bl i286a_selector
	str r0, [r9, #CPU_DS_BASE]
	str r0, [r9, #CPU_DS_FIX]
	mov pc, r11
	msegea_ss_p strh r0, [r9, #CPU_SS]
	bl i286a_selector
	str r0, [r9, #CPU_SS_BASE]
	str r0, [r9, #CPU_SS_FIX]
	NEXT_OPCODE

msegea_cs sub r8, r6, #(2 << 16)	msegea_cs sub r8, r6, #(2 << 16)
mov r6, #6	mov r6, #6
b i286a_localint	b i286a_localint


pop_ea POP #5	pop_ea POP #5
mov r6, r0	mov r6, r0
GETPCF8	GETPCF8
Line 895 call_far CPUWORK #13	Line 925 call_far CPUWORK #13
add r8, r8, #(2 << 16)	add r8, r8, #(2 << 16)
mov r4, r0 lsl #16	mov r4, r0 lsl #16
add r0, r5, r8 lsr #16	add r0, r5, r8 lsr #16
	ldrb r5, [r9, #CPU_MSW]
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r1, r0 lsl #4
strh r0, [r9, #CPU_CS]	strh r0, [r9, #CPU_CS]
str r1, [r9, #CPU_CS_BASE]	tst r5, #MSW_PE
	moveq r0, r0 lsl #4
	blne i286a_selector
	str r0, [r9, #CPU_CS_BASE]
mov r0, r8 lsl #16	mov r0, r8 lsl #16
orr r8, r4, r0 lsr #16	orr r8, r4, r0 lsr #16
mov pc, r11	mov pc, r11
Line 918 pushf CPUWORK #3	Line 951 pushf CPUWORK #3
b i286a_memorywrite_w	b i286a_memorywrite_w

popf POP #5	popf POP #5
	if 1
	mov r8, r8 lsr #16
	bic r1, r0, #&f000 ; i286
	and r2, r0, #(I_FLAG + T_FLAG)
	orr r8, r1, r8 lsl #16
	cmp r2, #(I_FLAG + T_FLAG)
	beq popf_withirq
	else
mov r2, #3	mov r2, #3
mov r8, r8 lsr #16	mov r8, r8 lsr #16
and r2, r2, r0 lsr #8	and r2, r2, r0 lsr #8
Line 926 popf POP #5	Line 967 popf POP #5
orr r8, r1, r8 lsl #16	orr r8, r1, r8 lsl #16
strb r2, [r9, #CPU_TRAP]	strb r2, [r9, #CPU_TRAP]
bne popf_withirq	bne popf_withirq
	endif
ldr r0, popf_pic	ldr r0, popf_pic
NOINTREXIT	NOINTREXIT
popf_withirq I286IRQCHECKTERM	popf_withirq I286IRQCHECKTERM
Line 1165 les_r16_ea GETPCF8	Line 1207 les_r16_ea GETPCF8
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r0, [r5, #CPU_REG]	strh r0, [r5, #CPU_REG]
add r0, r4, r6	add r0, r4, r6
	ldrb r4, [r9, #CPU_MSW]
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r1, r0 lsl #4
strh r0, [r9, #CPU_ES]	strh r0, [r9, #CPU_ES]
str r1, [r9, #CPU_ES_BASE]	tst r4, #MSW_PE
	moveq r0, r0 lsl #4
	blne i286a_selector
	str r0, [r9, #CPU_ES_BASE]
mov pc, r11	mov pc, r11
lr16_r mov r6, #6	lr16_r mov r6, #6
sub r8, r8, #(2 << 16)	sub r8, r8, #(2 << 16)
Line 1186 lds_r16_ea GETPCF8	Line 1231 lds_r16_ea GETPCF8
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r0, [r5, #CPU_REG]	strh r0, [r5, #CPU_REG]
add r0, r4, r6	add r0, r4, r6
	ldrb r4, [r9, #CPU_MSW]
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r1, r0 lsl #4
strh r0, [r9, #CPU_DS]	strh r0, [r9, #CPU_DS]
str r1, [r9, #CPU_DS_BASE]	tst r4, #MSW_PE
str r1, [r9, #CPU_DS_FIX]	moveq r0, r0 lsl #4
	blne i286a_selector
	str r0, [r9, #CPU_DS_BASE]
	str r0, [r9, #CPU_DS_FIX]
mov pc, r11	mov pc, r11

mov_ea8_d8 GETPCF8	mov_ea8_d8 GETPCF8
Line 1259 enterlv1 cmp r0, #1	Line 1307 enterlv1 cmp r0, #1
strh r2, [r9, #CPU_SP]	strh r2, [r9, #CPU_SP]
bl i286a_memorywrite_w	bl i286a_memorywrite_w
enterlv2 mov r1, r0, lsl #2	enterlv2 mov r1, r0, lsl #2
add r1, r1, #12	add r1, r1, #(12 + 4)
CPUWORK r1	CPUWORK r1
strh r4, [r9, #CPU_BP]	strh r4, [r9, #CPU_BP]
str r11, [sp, #-4]!	str r11, [sp, #-4]!
Line 1312 ret_far_d16 GETPC16	Line 1360 ret_far_d16 GETPC16
add r4, r4, #2	add r4, r4, #2
bl i286a_memoryread_w	bl i286a_memoryread_w
add r4, r6, r4	add r4, r6, r4
mov r1, r0 lsl #4	ldrb r1, [r9, #CPU_MSW]
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
strh r0, [r9, #CPU_CS]	strh r0, [r9, #CPU_CS]
str r1, [r9, #CPU_CS_BASE]	tst r1, #MSW_PE
	moveq r0, r0 lsl #4
	blne i286a_selector
	str r0, [r9, #CPU_CS_BASE]
mov pc, r11	mov pc, r11

ret_far ldrh r1, [r9, #CPU_SP]	ret_far ldrh r1, [r9, #CPU_SP]
Line 1331 ret_far ldrh r1, [r9, #CPU_SP]	Line 1382 ret_far ldrh r1, [r9, #CPU_SP]
add r0, r4, r5	add r0, r4, r5
add r4, r4, #2	add r4, r4, #2
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r1, r0 lsl #4	ldrb r1, [r9, #CPU_MSW]
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
strh r0, [r9, #CPU_CS]	strh r0, [r9, #CPU_CS]
str r1, [r9, #CPU_CS_BASE]	tst r1, #MSW_PE
	moveq r0, r0 lsl #4
	blne i286a_selector
	str r0, [r9, #CPU_CS_BASE]
mov pc, r11	mov pc, r11

int_03 CPUWORK #3	int_03 CPUWORK #3
Line 1352 into CPUWORK #4	Line 1406 into CPUWORK #4
mov r6, #4	mov r6, #4
b i286a_localint	b i286a_localint

iret bl extirq_pop	iret ldrh r1, [r9, #CPU_SP]
ldrh r1, [r9, #CPU_SP]
ldr r5, [r9, #CPU_SS_BASE]	ldr r5, [r9, #CPU_SS_BASE]
CPUWORK #31	CPUWORK #31
add r4, r1, #2	add r4, r1, #2
Line 1372 iret bl extirq_pop	Line 1425 iret bl extirq_pop
add r4, r4, #2	add r4, r4, #2
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
	if 1
	bic r1, r0, #&f000
	and r2, r0, #(I_FLAG + T_FLAG)
	orr r8, r1, r8
	cmp r2, #(I_FLAG + T_FLAG)
	beq iret_withirq
	else
mov r2, #3	mov r2, #3
bic r1, r0, #&f000 ; i286	bic r1, r0, #&f000 ; i286
and r2, r2, r0 lsr #8	and r2, r2, r0 lsr #8
Line 1379 iret bl extirq_pop	Line 1439 iret bl extirq_pop
ands r2, r2, r2 lsr #1	ands r2, r2, r2 lsr #1
strb r2, [r9, #CPU_TRAP]	strb r2, [r9, #CPU_TRAP]
bne iret_withirq	bne iret_withirq
	endif
ldr r0, iret_pic	ldr r0, iret_pic
NOINTREXIT	NOINTREXIT
iret_withirq I286IRQCHECKTERM	iret_withirq I286IRQCHECKTERM
Line 1562 jmp_far CPUWORK #11	Line 1623 jmp_far CPUWORK #11
mov r8, r0 lsl #16	mov r8, r0 lsl #16
add r0, r4, r5 lsr #16	add r0, r4, r5 lsr #16
bl i286a_memoryread_w	bl i286a_memoryread_w
	ldrb r1, [r9, #CPU_MSW]
add r8, r8, r6 lsr #16	add r8, r8, r6 lsr #16
mov r1, r0 lsl #4
strh r0, [r9, #CPU_CS]	strh r0, [r9, #CPU_CS]
str r1, [r9, #CPU_CS_BASE]	tst r1, #MSW_PE
	moveq r0, r0 lsl #4
	blne i286a_selector
	str r0, [r9, #CPU_CS_BASE]
mov pc, r11	mov pc, r11

in_al_dx CPUWORK #5	in_al_dx CPUWORK #5
Line 1621 stc CPUWORK #2	Line 1685 stc CPUWORK #2
mov pc, r11	mov pc, r11

cli CPUWORK #2	cli CPUWORK #2
	if 1
	bic r8, r8, #I_FLAG
	else
mov r0, #0	mov r0, #0
bic r8, r8, #I_FLAG	bic r8, r8, #I_FLAG
strb r0, [r9, #CPU_TRAP]	strb r0, [r9, #CPU_TRAP]
	endif
mov pc, r11	mov pc, r11

sti CPUWORK #2	sti CPUWORK #2
tst r8, #I_FLAG	tst r8, #I_FLAG
bne sti_noirq	bne sti_noirq
sti_set orr r8, r8, #I_FLAG	sti_set orr r8, r8, #I_FLAG
	if 1
	ldr r0, sti_pic
	tst r8, #T_FLAG
	bne sti_withirq
	else
mov r1, #(T_FLAG >> 8)	mov r1, #(T_FLAG >> 8)
ands r1, r1, r8 lsr #8	ands r1, r1, r8 lsr #8
ldr r0, sti_pic	ldr r0, sti_pic
strneb r1, [r9, #CPU_TRAP]	strneb r1, [r9, #CPU_TRAP]
bne sti_withirq	bne sti_withirq
PICEXISTINTR sti_noirq	endif
	PICEXISTINTR
bne sti_withirq	bne sti_withirq
sti_noirq NEXT_OPCODE	sti_noirq NEXT_OPCODE
sti_pic dcd pic	sti_pic dcd pic
Line 1667 i286a_step stmdb sp!, {r4 - r11, lr}	Line 1741 i286a_step stmdb sp!, {r4 - r11, lr}
mov r11, pc	mov r11, pc
mov pc, r1	mov pc, r1

bl dmap_i286	bl dmax86
CPUSV	CPUSV
ldmia sp!, {r4 - r11, pc}	ldmia sp!, {r4 - r11, pc}

Line 1709 i286awithdma adr r4, optbl1	Line 1783 i286awithdma adr r4, optbl1
add r8, r8, #(1 << 16)	add r8, r8, #(1 << 16)
mov r11, pc	mov r11, pc
mov pc, r1	mov pc, r1
bl dmap_i286	bl dmax86
CPUDBGL	CPUDBGL
cmp r7, #0	cmp r7, #0
ldrgt r5, [r9, #CPU_CS_BASE]	ldrgt r5, [r9, #CPU_CS_BASE]
Line 1724 i286awithtrap adr r4, optbl1	Line 1798 i286awithtrap adr r4, optbl1
add r8, r8, #(1 << 16)	add r8, r8, #(1 << 16)
mov r11, pc	mov r11, pc
mov pc, r1	mov pc, r1
bl dmap_i286	bl dmax86
and r0, r8, #(I_FLAG + T_FLAG)	and r0, r8, #(I_FLAG + T_FLAG)
cmp r0, #(I_FLAG + T_FLAG)	cmp r0, #(I_FLAG + T_FLAG)
beq i286a_trapint	bleq i286a_trapint
i286a_trapintr CPUSV	CPUSV
ldmia sp!, {r4 - r11, pc}	ldmia sp!, {r4 - r11, pc}

optbl1 dcd add_ea_r8 ; 00	optbl1 dcd add_ea_r8 ; 00

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.20
changed lines
	Added in v.1.29