np2/i286a/i286a_mn.s - diff

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Diff for /np2/i286a/i286a_mn.s between versions 1.15 and 1.23

version 1.15, 2003/12/21 23:27:08	version 1.23, 2004/01/29 00:27:29
Line 5	Line 5
INCLUDE i286aop.inc	INCLUDE i286aop.inc
INCLUDE i286aio.inc	INCLUDE i286aio.inc

IMPORT i286core	IMPORT i286acore
IMPORT iflags	IMPORT iflags
IMPORT i286a_localint	IMPORT i286a_localint
IMPORT i286a_trapint	IMPORT i286a_trapint
EXPORT i286a_trapintr	IMPORT i286a_selector
IMPORT i286a_ea	IMPORT i286a_ea
IMPORT i286a_lea	IMPORT i286a_lea
IMPORT i286a_a	IMPORT i286a_a
Line 465 pusha ldrh r4, [r9, #CPU_SP]	Line 465 pusha ldrh r4, [r9, #CPU_SP]
strh r0, [r9, #CPU_SP]	strh r0, [r9, #CPU_SP]
mov pc, r11	mov pc, r11

popa ldrh r4, [r9, #CPU_SP]	popa ldrh r1, [r9, #CPU_SP]
ldr r5, [r9, #CPU_SS_BASE]	ldr r5, [r9, #CPU_SS_BASE]
CPUWORK #19	CPUWORK #19
add r0, r5, r4	mov r4, r1 lsl #16
mov r4, r4 lsl #16	add r0, r5, r1
bl i286a_memoryread_w	bl i286a_memoryread_w
add r4, r4, #(2 << 16)	add r4, r4, #(2 << 16)
strh r0, [r9, #CPU_DI]	strh r0, [r9, #CPU_DI]
Line 504 popa ldrh r4, [r9, #CPU_SP]	Line 504 popa ldrh r4, [r9, #CPU_SP]
bound GETPCF8	bound GETPCF8
cmp r0, #&c0	cmp r0, #&c0
bcs bndreg	bcs bndreg
CPUWORK #13
R16DST r0, r12	R16DST r0, r12
	CPUWORK #13
ldrh r5, [r12, #CPU_REG]	ldrh r5, [r12, #CPU_REG]
bl i286a_a	bl i286a_a
add r4, r0, #2	add r4, r0, #2
Line 585 insb CPUWORK #5	Line 585 insb CPUWORK #5
ldrh r0, [r9, #CPU_DX]	ldrh r0, [r9, #CPU_DX]
CPUSV	CPUSV
bl iocore_inp8	bl iocore_inp8
CPULD
ldrh r2, [r9, #CPU_DI]	ldrh r2, [r9, #CPU_DI]
ldr r3, [r9, #CPU_ES_BASE]	ldr r3, [r9, #CPU_ES_BASE]
	CPULD
mov r1, r0	mov r1, r0
add r0, r2, r3	add r0, r3, r2
tst r8, #D_FLAG	tst r8, #D_FLAG
addeq r2, r2, #1	addeq r2, r2, #1
subne r2, r2, #1	subne r2, r2, #1
Line 601 insw CPUWORK #5	Line 601 insw CPUWORK #5
ldrh r0, [r9, #CPU_DX]	ldrh r0, [r9, #CPU_DX]
CPUSV	CPUSV
bl iocore_inp16	bl iocore_inp16
CPULD
ldrh r2, [r9, #CPU_DI]	ldrh r2, [r9, #CPU_DI]
ldr r3, [r9, #CPU_ES_BASE]	ldr r3, [r9, #CPU_ES_BASE]
	CPULD
mov r1, r0	mov r1, r0
add r0, r2, r3	add r0, r3, r2
tst r8, #D_FLAG	tst r8, #D_FLAG
addeq r2, r2, #2	addeq r2, r2, #2
subne r2, r2, #2	subne r2, r2, #2
Line 616 insw CPUWORK #5	Line 616 insw CPUWORK #5
outsb CPUWORK #3	outsb CPUWORK #3
ldrh r1, [r9, #CPU_SI]	ldrh r1, [r9, #CPU_SI]
ldr r2, [r9, #CPU_DS_FIX]	ldr r2, [r9, #CPU_DS_FIX]
add r0, r1, r2
tst r8, #D_FLAG	tst r8, #D_FLAG
addeq r1, r1, #1	addeq r3, r1, #1
subne r1, r1, #1	subne r3, r1, #1
strh r1, [r9, #CPU_SI]	add r0, r2, r1
	strh r3, [r9, #CPU_SI]
bl i286a_memoryread	bl i286a_memoryread
mov r1, r0	mov r1, r0
ldr r0, [r9, #CPU_DX]	ldr r0, [r9, #CPU_DX]
Line 632 outsb CPUWORK #3	Line 632 outsb CPUWORK #3
outsw CPUWORK #3	outsw CPUWORK #3
ldrh r1, [r9, #CPU_SI]	ldrh r1, [r9, #CPU_SI]
ldr r2, [r9, #CPU_DS_FIX]	ldr r2, [r9, #CPU_DS_FIX]
add r0, r1, r2
tst r8, #D_FLAG	tst r8, #D_FLAG
addeq r1, r1, #2	addeq r3, r1, #2
subne r1, r1, #2	subne r3, r1, #2
strh r1, [r9, #CPU_SI]	add r0, r2, r1
	strh r3, [r9, #CPU_SI]
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r1, r0	mov r1, r0
ldr r0, [r9, #CPU_DX]	ldr r0, [r9, #CPU_DX]
Line 665 jmps JMPS #7	Line 665 jmps JMPS #7
xchg_ea_r8 EAREG8 r6	xchg_ea_r8 EAREG8 r6
cmp r0, #&c0	cmp r0, #&c0
bcc xchgear8_1	bcc xchgear8_1
CPUWORK #3	R8SRC r0, r2
R8SRC r0, r5
ldrb r0, [r6, #CPU_REG]	ldrb r0, [r6, #CPU_REG]
ldrb r1, [r5, #CPU_REG]	ldrb r1, [r2, #CPU_REG]
strb r0, [r5, #CPU_REG]	CPUWORK #3
	strb r0, [r2, #CPU_REG]
strb r1, [r6, #CPU_REG]	strb r1, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
xchgear8_1 CPUWORK #5	xchgear8_1 bl i286a_ea
bl i286a_ea
cmp r0, #I286_MEMWRITEMAX	cmp r0, #I286_MEMWRITEMAX
bcs xchgear8_2	bcs xchgear8_2
ldrb r1, [r6, #CPU_REG]	ldrb r1, [r6, #CPU_REG]
ldrb r4, [r9, r0]	ldrb r4, [r9, r0]
	CPUWORK #5
strb r1, [r9, r0]	strb r1, [r9, r0]
strb r4, [r6, #CPU_REG]	strb r4, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
Line 685 xchgear8_2 mov r5, r0	Line 685 xchgear8_2 mov r5, r0
bl i286a_memoryread	bl i286a_memoryread
ldrb r1, [r6, #CPU_REG]	ldrb r1, [r6, #CPU_REG]
strb r0, [r6, #CPU_REG]	strb r0, [r6, #CPU_REG]
	CPUWORK #5
mov r0, r5	mov r0, r5
mov lr, r11	mov lr, r11
b i286a_memorywrite	b i286a_memorywrite
Line 692 xchgear8_2 mov r5, r0	Line 693 xchgear8_2 mov r5, r0
xchg_ea_r16 EAREG16 r6	xchg_ea_r16 EAREG16 r6
cmp r0, #&c0	cmp r0, #&c0
bcc xchgear16_1	bcc xchgear16_1
CPUWORK #3	R16SRC r0, r2
R16SRC r0, r5
ldrh r0, [r6, #CPU_REG]	ldrh r0, [r6, #CPU_REG]
ldrh r1, [r5, #CPU_REG]	ldrh r1, [r2, #CPU_REG]
strh r0, [r5, #CPU_REG]	CPUWORK #3
	strh r0, [r2, #CPU_REG]
strh r1, [r6, #CPU_REG]	strh r1, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
xchgear16_1 CPUWORK #5	xchgear16_1 bl i286a_ea
bl i286a_ea	WORDACC r0, xchgear16_2
tst r0, #1
bne xchgear16_2
cmp r0, #I286_MEMWRITEMAX
bcs xchgear16_2
ldrh r1, [r6, #CPU_REG]	ldrh r1, [r6, #CPU_REG]
ldrh r4, [r9, r0]	ldrh r4, [r9, r0]
	CPUWORK #5
strh r1, [r9, r0]	strh r1, [r9, r0]
strh r4, [r6, #CPU_REG]	strh r4, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
Line 714 xchgear16_2 mov r5, r0	Line 712 xchgear16_2 mov r5, r0
bl i286a_memoryread_w	bl i286a_memoryread_w
ldrh r1, [r6, #CPU_REG]	ldrh r1, [r6, #CPU_REG]
strh r0, [r6, #CPU_REG]	strh r0, [r6, #CPU_REG]
	CPUWORK #5
mov r0, r5	mov r0, r5
mov lr, r11	mov lr, r11
b i286a_memorywrite_w	b i286a_memorywrite_w
Line 721 xchgear16_2 mov r5, r0	Line 720 xchgear16_2 mov r5, r0
mov_ea_r8 EAREG8 r6	mov_ea_r8 EAREG8 r6
cmp r0, #&c0	cmp r0, #&c0
bcc movear8_1	bcc movear8_1
	ldrb r1, [r6, #CPU_REG]
	R8SRC r0, r2
CPUWORK #3	CPUWORK #3
R8SRC r0, r5	strb r1, [r2, #CPU_REG]
ldrb r0, [r6, #CPU_REG]
strb r0, [r5, #CPU_REG]
mov pc, r11	mov pc, r11
movear8_1 CPUWORK #5	movear8_1 CPUWORK #5
bl i286a_ea	bl i286a_ea
Line 735 movear8_1 CPUWORK #5	Line 734 movear8_1 CPUWORK #5
mov_ea_r16 EAREG16 r6	mov_ea_r16 EAREG16 r6
cmp r0, #&c0	cmp r0, #&c0
bcc movear16_1	bcc movear16_1
	ldrh r1, [r6, #CPU_REG]
	R16SRC r0, r2
CPUWORK #3	CPUWORK #3
R16SRC r0, r5	strh r1, [r2, #CPU_REG]
ldrh r0, [r6, #CPU_REG]
strh r0, [r5, #CPU_REG]
mov pc, r11	mov pc, r11
movear16_1 CPUWORK #5	movear16_1 CPUWORK #5
bl i286a_ea	bl i286a_ea
Line 757 mov_r16_ea REG16EA r6, #2, #5	Line 756 mov_r16_ea REG16EA r6, #2, #5
mov_ea_seg GETPCF8	mov_ea_seg GETPCF8
and r1, r0, #(3 << 3)	and r1, r0, #(3 << 3)
add r1, r9, r1 lsr #2	add r1, r9, r1 lsr #2
ldrh r5, [r1, #CPU_SEG]	ldrh r6, [r1, #CPU_SEG]
cmp r0, #&c0	cmp r0, #&c0
bcc measegm	bcc measegm
	R16SRC r0, r2
CPUWORK #2	CPUWORK #2
R16SRC r0, r4	strh r6, [r2, #CPU_REG]
strh r5, [r4, #CPU_REG]
mov pc, r11	mov pc, r11
measegm CPUWORK #3	measegm CPUWORK #3
bl i286a_ea	bl i286a_ea
mov r1, r5	mov r1, r6
mov lr, r11	mov lr, r11
b i286a_memorywrite_w	b i286a_memorywrite_w

Line 774 lea_r16_ea CPUWORK #3	Line 773 lea_r16_ea CPUWORK #3
GETPCF8	GETPCF8
cmp r0, #&c0	cmp r0, #&c0
bcs leareg	bcs leareg
R16DST r0, r5	R16DST r0, r6
bl i286a_lea	bl i286a_lea
strh r0, [r5, #CPU_REG]	strh r0, [r6, #CPU_REG]
mov pc, r11	mov pc, r11
leareg mov r6, #6	leareg mov r6, #6
sub r8, r8, #(2 << 16)	sub r8, r8, #(2 << 16)
b i286a_localint	b i286a_localint

mov_seg_ea GETPCF8	mov_seg_ea ldrh r6, [r9, #CPU_MSW]
adr r6, msegea_tbl	GETPCF8
	adr r2, msegea_tbl
and r1, r0, #(3 << 3)	and r1, r0, #(3 << 3)
mov r5, r8	tst r6, #MSW_PE
ldr r6, [r6, r1 lsr #1]	orrne r1, r1, #(4 << 3)
	mov r6, r8
	ldr r2, [r2, r1 lsr #1]
cmp r0, #&c0	cmp r0, #&c0
bcc msegeam	bcc msegeam
CPUWORK #2
R16SRC r0, r4	R16SRC r0, r4
	CPUWORK #2
ldrh r0, [r4, #CPU_REG]	ldrh r0, [r4, #CPU_REG]
mov pc, r6	mov pc, r2
msegeam CPUWORK #5	msegeam str r2, [sp, #-4]!
	CPUWORK #5
bl i286a_ea	bl i286a_ea
bl i286a_memoryread_w	ldr lr, [sp], #4
mov pc, r6	b i286a_memoryread_w
msegea_tbl dcd msegea_es	msegea_tbl dcd msegea_es
dcd msegea_cs	dcd msegea_cs
dcd msegea_ss	dcd msegea_ss
dcd msegea_ds	dcd msegea_ds
	dcd msegea_es_p
	dcd msegea_cs
	dcd msegea_ss_p
	dcd msegea_ds_p
msegea_es mov r1, r0 lsl #4	msegea_es mov r1, r0 lsl #4
strh r0, [r9, #CPU_ES]	strh r0, [r9, #CPU_ES]
str r1, [r9, #CPU_ES_BASE]	str r1, [r9, #CPU_ES_BASE]
Line 815 msegea_ss mov r1, r0 lsl #4	Line 822 msegea_ss mov r1, r0 lsl #4
str r1, [r9, #CPU_SS_BASE]	str r1, [r9, #CPU_SS_BASE]
str r1, [r9, #CPU_SS_FIX]	str r1, [r9, #CPU_SS_FIX]
NEXT_OPCODE	NEXT_OPCODE
msegea_cs sub r8, r5, #(2 << 16)
	msegea_es_p strh r0, [r9, #CPU_ES]
	bl i286a_selector
	str r0, [r9, #CPU_ES_BASE]
	mov pc, r11
	msegea_ds_p strh r0, [r9, #CPU_DS]
	bl i286a_selector
	str r0, [r9, #CPU_DS_BASE]
	str r0, [r9, #CPU_DS_FIX]
	mov pc, r11
	msegea_ss_p strh r0, [r9, #CPU_SS]
	bl i286a_selector
	str r0, [r9, #CPU_SS_BASE]
	str r0, [r9, #CPU_SS_FIX]
	NEXT_OPCODE

	msegea_cs sub r8, r6, #(2 << 16)
mov r6, #6	mov r6, #6
b i286a_localint	b i286a_localint


pop_ea POP #5	pop_ea POP #5
mov r6, r0	mov r6, r0
GETPCF8	GETPCF8
Line 835 popreg R16SRC r0, r1	Line 859 popreg R16SRC r0, r1

nopandbios sub r0, r8, #(1 << 16)	nopandbios sub r0, r8, #(1 << 16)
CPUWORK #3	CPUWORK #3
; ldr r5, [r9, #CPU_CS_BASE]	;; ldr r5, [r9, #CPU_CS_BASE]
add r0, r5, r0 lsr #16	add r0, r5, r0 lsr #16
cmp r0, #&0f8000	cmp r0, #&0f8000
movcc pc, r11	movcc pc, r11
Line 860 nopandbios sub r0, r8, #(1 << 16)	Line 884 nopandbios sub r0, r8, #(1 << 16)
str r3, [r9, #CPU_DS_FIX]	str r3, [r9, #CPU_DS_FIX]
mov pc, r11	mov pc, r11

cbw CPUWORK #2	cbw ldrb r0, [r9, #CPU_AL]
ldrb r0, [r9, #CPU_AL]	CPUWORK #2
mov r1, r0 lsl #24	mov r1, r0 lsl #24
mov r0, r1 asr #31	mov r0, r1 asr #31
strb r0, [r9, #CPU_AH]	strb r0, [r9, #CPU_AH]
mov pc, r11	mov pc, r11

cwd CPUWORK #2	cwd ldrb r0, [r9, #CPU_AH]
ldrb r0, [r9, #CPU_AH]	CPUWORK #2
mov r1, r0 lsl #24	mov r1, r0 lsl #24
mov r0, r1 asr #31	mov r0, r1 asr #31
strh r0, [r9, #CPU_DX]	strh r0, [r9, #CPU_DX]
Line 887 call_far CPUWORK #13	Line 911 call_far CPUWORK #13
mov r4, r4, lsr #16	mov r4, r4, lsr #16
mov r1, r12 lsr #16	mov r1, r12 lsr #16
add r0, r4, r5	add r0, r4, r5
bl i286a_memorywrite_w ; ip
ldr r5, [r9, #CPU_CS_BASE]	ldr r5, [r9, #CPU_CS_BASE]
	bl i286a_memorywrite_w ; ip
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
add r0, r5, r8 lsr #16	add r0, r5, r8 lsr #16
bl i286a_memoryread_w ; newip	bl i286a_memoryread_w ; newip
Line 918 pushf CPUWORK #3	Line 942 pushf CPUWORK #3
b i286a_memorywrite_w	b i286a_memorywrite_w

popf POP #5	popf POP #5
	if 1
	mov r8, r8 lsr #16
	bic r1, r0, #&f000 ; i286
	and r2, r0, #(I_FLAG + T_FLAG)
	orr r8, r1, r8 lsl #16
	cmp r2, #(I_FLAG + T_FLAG)
	beq popf_withirq
	else
mov r2, #3	mov r2, #3
mov r8, r8 lsr #16	mov r8, r8 lsr #16
and r2, r2, r0 lsr #8	and r2, r2, r0 lsr #8
Line 926 popf POP #5	Line 958 popf POP #5
orr r8, r1, r8 lsl #16	orr r8, r1, r8 lsl #16
strb r2, [r9, #CPU_TRAP]	strb r2, [r9, #CPU_TRAP]
bne popf_withirq	bne popf_withirq
	endif
ldr r0, popf_pic	ldr r0, popf_pic
NOINTREXIT	NOINTREXIT
popf_withirq I286IRQCHECKTERM	popf_withirq I286IRQCHECKTERM
popf_pic dcd pic	popf_pic dcd pic

sahf CPUWORK #2	sahf ldrb r0, [r9, #CPU_AH]
ldrb r0, [r9, #CPU_AH]	CPUWORK #2
bic r8, r8, #&ff	bic r8, r8, #&ff
orr r8, r0, r8	orr r8, r8, r0
mov pc, r11	mov pc, r11

lahf CPUWORK #2	lahf CPUWORK #2
Line 943 lahf CPUWORK #2	Line 976 lahf CPUWORK #2


mov_al_m8 CPUWORK #5	mov_al_m8 CPUWORK #5
ldr r5, [r9, #CPU_DS_FIX]	ldr r6, [r9, #CPU_DS_FIX]
GETPC16	GETPC16
add r0, r5, r0	add r0, r0, r6
bl i286a_memoryread	bl i286a_memoryread
strb r0, [r9, #CPU_AL]	strb r0, [r9, #CPU_AL]
mov pc, r11	mov pc, r11

mov_ax_m16 CPUWORK #5	mov_ax_m16 CPUWORK #5
ldr r5, [r9, #CPU_DS_FIX]	ldr r6, [r9, #CPU_DS_FIX]
GETPC16	GETPC16
add r0, r5, r0	add r0, r0, r6
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r0, [r9, #CPU_AX]	strh r0, [r9, #CPU_AX]
mov pc, r11	mov pc, r11

mov_m8_al CPUWORK #5	mov_m8_al CPUWORK #5
ldr r5, [r9, #CPU_DS_FIX]	ldr r6, [r9, #CPU_DS_FIX]
GETPC16	GETPC16
ldrb r1, [r9, #CPU_AL]	ldrb r1, [r9, #CPU_AL]
add r0, r5, r0	add r0, r0, r6
mov lr, r11	mov lr, r11
b i286a_memorywrite	b i286a_memorywrite

mov_m16_ax CPUWORK #5	mov_m16_ax CPUWORK #5
ldr r5, [r9, #CPU_DS_FIX]	ldr r6, [r9, #CPU_DS_FIX]
GETPC16	GETPC16
ldrh r1, [r9, #CPU_AX]	ldrh r1, [r9, #CPU_AX]
add r0, r5, r0	add r0, r0, r6
mov lr, r11	mov lr, r11
b i286a_memorywrite_w	b i286a_memorywrite_w

movsb CPUWORK #5	movsb CPUWORK #5
ldrh r5, [r9, #CPU_SI]	ldrh r6, [r9, #CPU_SI]
ldr r0, [r9, #CPU_DS_FIX]	ldr r0, [r9, #CPU_DS_FIX]
tst r8, #D_FLAG	tst r8, #D_FLAG
moveq r4, #1	moveq r4, #1
movne r4, #-1	movne r4, #-1
add r0, r5, r0	add r0, r6, r0
bl i286a_memoryread	bl i286a_memoryread
ldrh r3, [r9, #CPU_DI]	ldrh r3, [r9, #CPU_DI]
ldr r2, [r9, #CPU_ES_BASE]	ldr r2, [r9, #CPU_ES_BASE]
add r5, r5, r4	add r6, r6, r4
mov r1, r0	mov r1, r0
add r0, r3, r2	add r0, r3, r2
add r3, r3, r4	add r3, r3, r4
strh r5, [r9, #CPU_SI]	strh r6, [r9, #CPU_SI]
strh r3, [r9, #CPU_DI]	strh r3, [r9, #CPU_DI]
mov lr, r11	mov lr, r11
b i286a_memorywrite	b i286a_memorywrite

movsw CPUWORK #5	movsw CPUWORK #5
ldrh r5, [r9, #CPU_SI]	ldrh r6, [r9, #CPU_SI]
ldr r0, [r9, #CPU_DS_FIX]	ldr r0, [r9, #CPU_DS_FIX]
tst r8, #D_FLAG	tst r8, #D_FLAG
moveq r4, #2	moveq r4, #2
movne r4, #-2	movne r4, #-2
add r0, r5, r0	add r0, r6, r0
bl i286a_memoryread_w	bl i286a_memoryread_w
ldrh r3, [r9, #CPU_DI]	ldrh r3, [r9, #CPU_DI]
ldr r2, [r9, #CPU_ES_BASE]	ldr r2, [r9, #CPU_ES_BASE]
add r5, r5, r4	add r6, r6, r4
mov r1, r0	mov r1, r0
add r0, r3, r2	add r0, r3, r2
add r3, r3, r4	add r3, r3, r4
strh r5, [r9, #CPU_SI]	strh r6, [r9, #CPU_SI]
strh r3, [r9, #CPU_DI]	strh r3, [r9, #CPU_DI]
mov lr, r11	mov lr, r11
b i286a_memorywrite_w	b i286a_memorywrite_w

cmpsb CPUWORK #8	cmpsb ldrh r5, [r9, #CPU_SI]
ldrh r5, [r9, #CPU_SI]
ldr r0, [r9, #CPU_DS_FIX]	ldr r0, [r9, #CPU_DS_FIX]
;	ldr r4, [r9, #CPU_ES_BASE]
;	CPUWORK #8
add r0, r5, r0	add r0, r0, r5
bl i286a_memoryread	bl i286a_memoryread
ldr r2, [r9, #CPU_ES_BASE]
ldrh r3, [r9, #CPU_DI]	ldrh r3, [r9, #CPU_DI]
mov r6, r0	mov r6, r0
and r12, r8, #D_FLAG	and r12, r8, #D_FLAG
mov r12, r12 lsr #(10 - 1)	mov r12, r12 lsr #(10 - 1)
add r0, r2, r3	add r0, r3, r4
rsb r2, r12, #1	rsb r2, r12, #1
add r5, r2, r5	add r5, r2, r5
add r3, r2, r3	add r3, r2, r3
Line 1034 cmpsb CPUWORK #8	Line 1065 cmpsb CPUWORK #8
SUB8 r6, r0	SUB8 r6, r0
mov pc, r11	mov pc, r11

cmpsw CPUWORK #8	cmpsw ldrh r5, [r9, #CPU_SI]
ldrh r5, [r9, #CPU_SI]
ldr r0, [r9, #CPU_DS_FIX]	ldr r0, [r9, #CPU_DS_FIX]
;	ldr r4, [r9, #CPU_ES_BASE]
;	CPUWORK #8
add r0, r5, r0	add r0, r0, r5
bl i286a_memoryread_w	bl i286a_memoryread_w
ldr r2, [r9, #CPU_ES_BASE]
ldrh r3, [r9, #CPU_DI]	ldrh r3, [r9, #CPU_DI]
mov r6, r0	mov r6, r0
and r12, r8, #D_FLAG	and r12, r8, #D_FLAG
mov r12, r12 lsr #(10 - 2)	mov r12, r12 lsr #(10 - 2)
add r0, r2, r3	add r0, r3, r4
rsb r2, r12, #2	rsb r2, r12, #2
add r5, r2, r5	add r5, r2, r5
add r3, r2, r3	add r3, r2, r3
Line 1294 leave ldrh r1, [r9, #CPU_BP]	Line 1323 leave ldrh r1, [r9, #CPU_BP]
ldr r0, [r9, #CPU_SS_BASE]	ldr r0, [r9, #CPU_SS_BASE]
CPUWORK #5	CPUWORK #5
add r4, r1, #2	add r4, r1, #2
add r0, r1, r0	add r0, r0, r1
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
strh r0, [r9, #CPU_BP]	strh r0, [r9, #CPU_BP]
mov pc, r11	mov pc, r11

ret_far_d16 CPUWORK #15	ret_far_d16 GETPC16
GETPC16
mov r6, r0
ldrh r4, [r9, #CPU_SP]	ldrh r4, [r9, #CPU_SP]
ldr r5, [r9, #CPU_SS_BASE]	ldr r5, [r9, #CPU_SS_BASE]
;	mov r6, r0
;	CPUWORK #15
add r0, r4, r5	add r0, r5, r4
add r4, r4, #2	add r4, r4, #2
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r8, r8 lsl #16	mov r8, r8 lsl #16
Line 1324 ret_far_d16 CPUWORK #15	Line 1351 ret_far_d16 CPUWORK #15
str r1, [r9, #CPU_CS_BASE]	str r1, [r9, #CPU_CS_BASE]
mov pc, r11	mov pc, r11

ret_far CPUWORK #15	ret_far ldrh r1, [r9, #CPU_SP]
ldrh r4, [r9, #CPU_SP]
ldr r5, [r9, #CPU_SS_BASE]	ldr r5, [r9, #CPU_SS_BASE]
;	CPUWORK #15
add r0, r4, r5	add r4, r1, #2
add r4, r4, #2	add r0, r5, r1
bl i286a_memoryread_w	bl i286a_memoryread_w
mov r8, r8 lsl #16	mov r8, r8 lsl #16
mov r8, r8 lsr #16	mov r8, r8 lsr #16
Line 1359 into CPUWORK #4	Line 1385 into CPUWORK #4
mov r6, #4	mov r6, #4
b i286a_localint	b i286a_localint

iret bl extirq_pop	iret ldrh r1, [r9, #CPU_SP]
CPUWORK #31
ldrh r1, [r9, #CPU_SP]
ldr r5, [r9, #CPU_SS_BASE]	ldr r5, [r9, #CPU_SS_BASE]
;	CPUWORK #31
add r4, r1, #2	add r4, r1, #2
add r0, r1, r5	add r0, r5, r1
bl i286a_memoryread_w	bl i286a_memoryread_w
bic r4, r4, #(1 << 16)	bic r4, r4, #(1 << 16)
mov r8, r0 lsl #16	mov r8, r0 lsl #16
Line 1380 iret bl extirq_pop	Line 1404 iret bl extirq_pop
add r4, r4, #2	add r4, r4, #2
bl i286a_memoryread_w	bl i286a_memoryread_w
strh r4, [r9, #CPU_SP]	strh r4, [r9, #CPU_SP]
	if 1
	bic r1, r0, #&f000
	and r2, r0, #(I_FLAG + T_FLAG)
	orr r8, r1, r8
	cmp r2, #(I_FLAG + T_FLAG)
	beq iret_withirq
	else
mov r2, #3	mov r2, #3
bic r1, r0, #&f000 ; i286	bic r1, r0, #&f000 ; i286
and r2, r2, r0 lsr #8	and r2, r2, r0 lsr #8
Line 1387 iret bl extirq_pop	Line 1418 iret bl extirq_pop
ands r2, r2, r2 lsr #1	ands r2, r2, r2 lsr #1
strb r2, [r9, #CPU_TRAP]	strb r2, [r9, #CPU_TRAP]
bne iret_withirq	bne iret_withirq
	endif
ldr r0, iret_pic	ldr r0, iret_pic
NOINTREXIT	NOINTREXIT
iret_withirq I286IRQCHECKTERM	iret_withirq I286IRQCHECKTERM
Line 1420 aamzero sub r8, r8, #(2 << 16)	Line 1452 aamzero sub r8, r8, #(2 << 16)
mov r6, #0	mov r6, #0
b i286a_localint	b i286a_localint

aad CPUWORK #14	aad ldrh r6, [r9, #CPU_AX]
GETPCF8	GETPCF8
ldrh r1, [r9, #CPU_AX]	mov r2, r6 lsr #8
	mla r3, r2, r0, r6
bic r8, r8, #(S_FLAG + Z_FLAG + P_FLAG)	bic r8, r8, #(S_FLAG + Z_FLAG + P_FLAG)
;
mov r2, r1 lsr #8
mla r3, r2, r0, r1
;
and r1, r3, #&ff	and r1, r3, #&ff
;	ldrb r2, [r1, r10]
ldrb r2, [r10, r1]
strh r1, [r9, #CPU_AX]	strh r1, [r9, #CPU_AX]
;	CPUWORK #14
orr r8, r2, r8	orr r8, r2, r8
mov pc, r11	mov pc, r11

Line 1508 jcxz ldrh r0, [r9, #CPU_CX]	Line 1536 jcxz ldrh r0, [r9, #CPU_CX]
mov pc, r11	mov pc, r11
jcxzj JMPS #8	jcxzj JMPS #8

in_al_d8 CPUWORK #5	in_al_d8 GETPCF8
GETPCF8	CPUWORK #5
add r3, r0, r8 lsr #16	add r3, r5, r8 lsr #16
CPUSV	CPUSV
str r3, [r9, #CPU_INPUT]	str r3, [r9, #CPU_INPUT]
bl iocore_inp8	bl iocore_inp8
Line 1544 out_d8_ax CPUWORK #3	Line 1572 out_d8_ax CPUWORK #3
CPULD	CPULD
mov pc, r11	mov pc, r11

call_near CPUWORK #7	call_near GETPC16
GETPC16
ldrh r2, [r9, #CPU_SP]	ldrh r2, [r9, #CPU_SP]
ldr r3, [r9, #CPU_SS_BASE]	ldr r3, [r9, #CPU_SS_BASE]
;	CPUWORK #7
sub r1, r2, #2	sub r1, r2, #2
mov r2, r1 lsl #16	mov r2, r1 lsl #16
strh r1, [r9, #CPU_SP]	strh r1, [r9, #CPU_SP]
Line 1634 stc CPUWORK #2	Line 1661 stc CPUWORK #2
mov pc, r11	mov pc, r11

cli CPUWORK #2	cli CPUWORK #2
	if 1
	bic r8, r8, #I_FLAG
	else
mov r0, #0	mov r0, #0
bic r8, r8, #I_FLAG	bic r8, r8, #I_FLAG
strb r0, [r9, #CPU_TRAP]	strb r0, [r9, #CPU_TRAP]
	endif
mov pc, r11	mov pc, r11

sti CPUWORK #2	sti CPUWORK #2
tst r8, #I_FLAG	tst r8, #I_FLAG
bne sti_noirq	bne sti_noirq
sti_set orr r8, r8, #I_FLAG	sti_set orr r8, r8, #I_FLAG
	if 1
	ldr r0, sti_pic
	tst r8, #T_FLAG
	bne sti_withirq
	else
mov r1, #(T_FLAG >> 8)	mov r1, #(T_FLAG >> 8)
ands r1, r1, r8 lsr #8	ands r1, r1, r8 lsr #8
ldr r0, sti_pic	ldr r0, sti_pic
strneb r1, [r9, #CPU_TRAP]	strneb r1, [r9, #CPU_TRAP]
bne sti_withirq	bne sti_withirq
PICEXISTINTR sti_noirq	endif
	PICEXISTINTR
bne sti_withirq	bne sti_withirq
sti_noirq NEXT_OPCODE	sti_noirq NEXT_OPCODE
sti_pic dcd pic	sti_pic dcd pic
Line 1691 i286a stmdb sp!, {r4 - r11, lr}	Line 1728 i286a stmdb sp!, {r4 - r11, lr}
ldr r10, ias_r10	ldr r10, ias_r10
CPULD	CPULD
ldr r5, [r9, #CPU_CS_BASE]	ldr r5, [r9, #CPU_CS_BASE]
ldr r1, [r2, #DMAC_WORKING]	ldrb r1, [r2, #DMAC_WORKING]
and r0, r8, #(I_FLAG + T_FLAG)	and r0, r8, #(I_FLAG + T_FLAG)
cmp r0, #(I_FLAG + T_FLAG)	cmp r0, #(I_FLAG + T_FLAG)
beq i286awithtrap	beq i286awithtrap
cmp r1, #0	cmp r1, #0
bne i286awithdma	bne i286awithdma
adr r4, optbl1	i286a_lp adr r4, optbl1
i286a_lp add r0, r5, r8 lsr #16	add r0, r5, r8 lsr #16
GETR0	GETR0
ldr r1, [r4, r0 lsl #2]	ldr r1, [r4, r0 lsl #2]
add r8, r8, #(1 << 16)	add r8, r8, #(1 << 16)
mov r11, pc	mov r11, pc
mov pc, r1	mov pc, r1
CPUDBGL	CPUDBGL
ldr r5, [r9, #CPU_CS_BASE]
adr r4, optbl1
cmp r7, #0	cmp r7, #0
	ldrgt r5, [r9, #CPU_CS_BASE]
bgt i286a_lp	bgt i286a_lp
CPUSV	CPUSV
ldmia sp!, {r4 - r11, pc}	ldmia sp!, {r4 - r11, pc}

ias_r9 dcd i286core + CPU_SIZE	ias_r9 dcd i286acore + CPU_SIZE
ias_r1 dcd dmac	ias_r1 dcd dmac
ias_r10 dcd iflags	ias_r10 dcd iflags

i286awithdma adr r4, optbl1	i286awithdma adr r4, optbl1
i286awdma_lp add r0, r5, r8 lsr #16	add r0, r5, r8 lsr #16
GETR0	GETR0
ldr r1, [r4, r0 lsl #2]	ldr r1, [r4, r0 lsl #2]
add r8, r8, #(1 << 16)	add r8, r8, #(1 << 16)
Line 1725 i286awdma_lp add r0, r5, r8 lsr #16	Line 1761 i286awdma_lp add r0, r5, r8 lsr #16
mov pc, r1	mov pc, r1
bl dmap_i286	bl dmap_i286
CPUDBGL	CPUDBGL
ldr r5, [r9, #CPU_CS_BASE]
adr r4, optbl1
cmp r7, #0	cmp r7, #0
bgt i286awdma_lp	ldrgt r5, [r9, #CPU_CS_BASE]
	bgt i286awithdma
CPUSV	CPUSV
ldmia sp!, {r4 - r11, pc}	ldmia sp!, {r4 - r11, pc}

i286awithtrap adr r4, optbl1	i286awithtrap adr r4, optbl1
i286awtrp_lp add r0, r5, r8 lsr #16	add r0, r5, r8 lsr #16
GETR0	GETR0
ldr r1, [r4, r0 lsl #2]	ldr r1, [r4, r0 lsl #2]
add r8, r8, #(1 << 16)	add r8, r8, #(1 << 16)
Line 1742 i286awtrp_lp add r0, r5, r8 lsr #16	Line 1777 i286awtrp_lp add r0, r5, r8 lsr #16
bl dmap_i286	bl dmap_i286
and r0, r8, #(I_FLAG + T_FLAG)	and r0, r8, #(I_FLAG + T_FLAG)
cmp r0, #(I_FLAG + T_FLAG)	cmp r0, #(I_FLAG + T_FLAG)
beq i286a_trapint	bleq i286a_trapint
i286a_trapintr CPUSV	CPUSV
ldmia sp!, {r4 - r11, pc}	ldmia sp!, {r4 - r11, pc}

optbl1 dcd add_ea_r8 ; 00	optbl1 dcd add_ea_r8 ; 00
Line 1954 optbl1 dcd add_ea_r8 ; 00	Line 1989 optbl1 dcd add_ea_r8 ; 00
dcd i286asft16_d8	dcd i286asft16_d8
dcd ret_near_d16	dcd ret_near_d16
dcd ret_near	dcd ret_near
dcd les_r16_ea ; (now testing i286a_a)	dcd les_r16_ea
dcd lds_r16_ea ; (now testing i286a_a)	dcd lds_r16_ea
dcd mov_ea8_d8	dcd mov_ea8_d8
dcd mov_ea16_d16	dcd mov_ea16_d16
dcd enter	dcd enter

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