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| version 1.1, 2003/12/18 19:14:08 | version 1.3, 2003/12/21 23:27:08 |
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| Line 3 | Line 3 |
| $label GETPC8 | $label GETPC8 |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label ldr r0, [r9, #CPU_CS_BASE] |
| add r0, r0, r8 lsr #16 | add r0, r0, r8 lsr #16 |
| bl i286_memoryread | bl i286a_memoryread |
| add r8, r8, #(1 << 16) | add r8, r8, #(1 << 16) |
| MEND | MEND |
| Line 11 $label ldr r0, [r9, #CPU_CS_BASE] | Line 11 $label ldr r0, [r9, #CPU_CS_BASE] |
| $label GETPC16 | $label GETPC16 |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label ldr r0, [r9, #CPU_CS_BASE] |
| add r0, r0, r8 lsr #16 | add r0, r0, r8 lsr #16 |
| bl i286_memoryread_w | bl i286a_memoryread_w |
| add r8, r8, #(2 << 16) | add r8, r8, #(2 << 16) |
| MEND | MEND |
| MACRO | |
| $label GETR0 | |
| $label cmp r0, #I286_MEMWRITEMAX | |
| ldrccb r0, [r0, r9] | |
| blcs i286a_memoryread | |
| MEND | |
| MACRO | |
| $label GETPCF8 | |
| $label add r0, r5, r8 lsr #16 | |
| cmp r0, #I286_MEMWRITEMAX | |
| ldrccb r0, [r0, r9] | |
| blcs i286a_memoryread | |
| add r8, r8, #(1 << 16) | |
| MEND | |
| MACRO | MACRO |
| $label R8SRC $op, $out | $label R8SRC $op, $out |
| $label and $out, $op, #3 | $label and $out, $op, #3 |
| add $out, r9, $out lsl #1 | |
| tst $op, #(1 << 2) | tst $op, #(1 << 2) |
| add $out, r9, $out lsl #1 | |
| addne $out, $out, #1 | addne $out, $out, #1 |
| MEND | MEND |
| MACRO | MACRO |
| $label R8DST $op, $out | $label R8DST $op, $out |
| $label and $out, $op, #(6 << 2) | $label and $out, $op, #(6 << 2) |
| add $out, r9, $out lsr #2 | |
| tst $op, #(1 << 5) | tst $op, #(1 << 5) |
| add $out, r9, $out lsr #2 | |
| addne $out, $out, #1 | addne $out, $out, #1 |
| MEND | MEND |
| MACRO | MACRO |
| $label EAREG8 $src | $label EAREG8 $src |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label add r0, r5, r8 lsr #16 |
| add r0, r0, r8 lsr #16 | GETR0 |
| bl i286_memoryread | |
| add r8, r8, #(1 << 16) | |
| and $src, r0, #(6 << 2) | and $src, r0, #(6 << 2) |
| add r8, r8, #(1 << 16) | |
| add $src, r9, $src lsr #2 | add $src, r9, $src lsr #2 |
| tst r0, #(1 << 5) | tst r0, #(1 << 5) |
| addne $src, $src, #1 | addne $src, $src, #1 |
| Line 46 $label ldr r0, [r9, #CPU_CS_BASE] | Line 63 $label ldr r0, [r9, #CPU_CS_BASE] |
| MACRO | MACRO |
| $label REG8EA $dst, $regclk, $memclk | $label REG8EA $dst, $regclk, $memclk |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label add r0, r5, r8 lsr #16 |
| add r0, r0, r8 lsr #16 | GETR0 |
| bl i286_memoryread | |
| add r8, r8, #(1 << 16) | add r8, r8, #(1 << 16) |
| R8DST r0, $dst | R8DST r0, $dst |
| cmp r0, #&c0 | cmp r0, #&c0 |
| Line 59 $label ldr r0, [r9, #CPU_CS_BASE] | Line 75 $label ldr r0, [r9, #CPU_CS_BASE] |
| b $label.2 | b $label.2 |
| $label.1 CPUWORK $memclk | $label.1 CPUWORK $memclk |
| bl i286a_ea | bl i286a_ea |
| bl i286_memoryread | bl i286a_memoryread |
| $label.2 | $label.2 |
| MEND | MEND |
| Line 78 $label and $out, $op, #(7 << 3) | Line 94 $label and $out, $op, #(7 << 3) |
| MACRO | MACRO |
| $label EAREG16 $src | $label EAREG16 $src |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label add r0, r5, r8 lsr #16 |
| add r0, r0, r8 lsr #16 | GETR0 |
| bl i286_memoryread | |
| add r8, r8, #(1 << 16) | |
| and $src, r0, #(7 << 3) | and $src, r0, #(7 << 3) |
| add r8, r8, #(1 << 16) | |
| add $src, r9, $src lsr #2 | add $src, r9, $src lsr #2 |
| MEND | MEND |
| MACRO | MACRO |
| $label REG16EA $dst, $regclk, $memclk | $label REG16EA $dst, $regclk, $memclk |
| $label ldr r0, [r9, #CPU_CS_BASE] | $label add r0, r5, r8 lsr #16 |
| add r0, r0, r8 lsr #16 | GETR0 |
| bl i286_memoryread | and $dst, r0, #(7 << 3) |
| add r8, r8, #(1 << 16) | add r8, r8, #(1 << 16) |
| R16DST r0, $dst | add $dst, r9, $dst lsr #2 |
| cmp r0, #&c0 | cmp r0, #&c0 |
| bcc $label.1 | bcc $label.1 |
| CPUWORK $regclk | CPUWORK $regclk |
| Line 101 $label ldr r0, [r9, #CPU_CS_BASE] | Line 116 $label ldr r0, [r9, #CPU_CS_BASE] |
| b $label.2 | b $label.2 |
| $label.1 CPUWORK $memclk | $label.1 CPUWORK $memclk |
| bl i286a_ea | bl i286a_ea |
| bl i286_memoryread_w | bl i286a_memoryread_w |
| $label.2 | $label.2 |
| MEND | MEND |