|
version 1.6, 2003/12/20 10:27:55
|
version 1.13, 2005/03/11 15:12:57
|
|
Line 3
|
Line 3
|
| INCLUDE i286amem.inc |
INCLUDE i286amem.inc |
| INCLUDE i286aio.inc |
INCLUDE i286aio.inc |
| |
|
| IMPORT memfn |
|
| IMPORT vramupdate |
IMPORT vramupdate |
| IMPORT tramupdate |
IMPORT tramupdate |
| |
|
| IMPORT egc_write |
IMPORT egc_writebyte |
| IMPORT egc_read |
IMPORT egc_readbyte |
| IMPORT egc_write_w |
IMPORT egc_writeword |
| IMPORT egc_read_w |
IMPORT egc_readword |
| |
|
| EXPORT i286_rd |
EXPORT memfn |
| EXPORT i286_rdex |
EXPORT i286_memorymap |
| EXPORT i286w_rd |
EXPORT i286_vram_dispatch |
| EXPORT i286w_rdex |
|
| EXPORT i286_wt |
|
| EXPORT i286_wtex |
|
| EXPORT i286w_wt |
|
| EXPORT i286w_wtex |
|
| |
|
| EXPORT tram_rd |
|
| EXPORT tramw_rd |
|
| EXPORT tram_wt |
|
| EXPORT tramw_wt |
|
| |
|
| EXPORT vram_r0 |
|
| EXPORT vram_r1 |
|
| EXPORT vramw_r0 |
|
| EXPORT vramw_r1 |
|
| EXPORT vram_w0 |
|
| EXPORT vram_w1 |
|
| EXPORT vramw_w0 |
|
| EXPORT vramw_w1 |
|
| |
|
| EXPORT grcg_tcr0 |
|
| EXPORT grcg_tcr1 |
|
| EXPORT grcgw_tcr0 |
|
| EXPORT grcgw_tcr1 |
|
| |
|
| EXPORT grcg_tdw0 |
|
| EXPORT grcg_tdw1 |
|
| EXPORT grcgw_tdw0 |
|
| EXPORT grcgw_tdw1 |
|
| |
|
| EXPORT grcg_rmw0 |
|
| EXPORT grcg_rmw1 |
|
| EXPORT grcgw_rmw0 |
|
| EXPORT grcgw_rmw1 |
|
| |
|
| ;; EXPORT egc_rd |
|
| ;; EXPORT egcw_rd |
|
| ;; EXPORT egc_wt |
|
| ;; EXPORT egcw_wt |
|
| |
|
| EXPORT emmc_rd |
|
| EXPORT emmcw_rd |
|
| EXPORT emmc_wt |
|
| EXPORT emmcw_wt |
|
| |
|
| EXPORT i286_itf |
|
| EXPORT i286w_itf |
|
| |
|
| EXPORT i286_wn |
|
| EXPORT i286w_wn |
|
| |
|
| EXPORT i286_nonram_r |
EXPORT i286_nonram_r |
| EXPORT i286_nonram_rw |
EXPORT i286_nonram_rw |
| |
|
| |
AREA .data, DATA, READWRITE |
| |
|
| |
memfn dcd i286_rdex ; 00 |
| |
dcd i286_rdex |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd ; 20 |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd ; 40 |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd ; 60 |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd ; 80 |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd tram_rd ; a0 |
| |
dcd vram_r0 |
| |
dcd vram_r0 |
| |
dcd vram_r0 |
| |
dcd emmc_rd ; c0 |
| |
dcd emmc_rd |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd vram_r0 ; e0 |
| |
dcd i286_rd |
| |
dcd i286_rd |
| |
dcd i286_rb |
| |
|
| |
dcd i286_wtex ; 00 |
| |
dcd i286_wtex |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt ; 20 |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt ; 40 |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt ; 60 |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt ; 80 |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd i286_wt |
| |
dcd tram_wt ; a0 |
| |
dcd vram_w0 |
| |
dcd vram_w0 |
| |
dcd vram_w0 |
| |
dcd emmc_wt ; c0 |
| |
dcd emmc_wt |
| |
dcd i286_wn |
| |
dcd i286_wn |
| |
dcd vram_w0 ; e0 |
| |
dcd i286_wn |
| |
dcd i286_wn |
| |
dcd i286_wn |
| |
|
| |
dcd i286w_rdex ; 00 |
| |
dcd i286w_rdex |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd ; 20 |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd ; 40 |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd ; 60 |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd ; 80 |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd tramw_rd ; a0 |
| |
dcd vramw_r0 |
| |
dcd vramw_r0 |
| |
dcd vramw_r0 |
| |
dcd emmcw_rd ; c0 |
| |
dcd emmcw_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd vramw_r0 ; e0 |
| |
dcd i286w_rd |
| |
dcd i286w_rd |
| |
dcd i286w_rb |
| |
|
| |
dcd i286w_wtex ; 00 |
| |
dcd i286w_wtex |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt ; 20 |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt ; 40 |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt ; 60 |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt ; 80 |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd i286w_wt |
| |
dcd tramw_wt ; a0 |
| |
dcd vramw_w0 |
| |
dcd vramw_w0 |
| |
dcd vramw_w0 |
| |
dcd emmcw_wt ; c0 |
| |
dcd emmcw_wt |
| |
dcd i286w_wn |
| |
dcd i286w_wn |
| |
dcd vramw_w0 ; e0 |
| |
dcd i286w_wn |
| |
dcd i286w_wn |
| |
dcd i286w_wn |
| |
|
| |
|
| AREA .text, CODE, READONLY |
AREA .text, CODE, READONLY |
| |
|
| ; ---- memory... |
; ---- memory... |
|
Line 910 grcgw_clock ;; ldr r3, grww_vramop
|
Line 994 grcgw_clock ;; ldr r3, grww_vramop
|
| mov pc, lr |
mov pc, lr |
| |
|
| |
|
| |
|
| ; ---- egc |
; ---- egc |
| |
|
| egc_rd ldrb r3, [r9, #MEMWAIT_GRCG] |
egc_rd ldrb r3, [r9, #MEMWAIT_GRCG] |
| CPUWORK r3 |
CPUWORK r3 |
| b egc_read |
b egc_readbyte |
| |
|
| |
|
| egcw_rd |
egcw_rd ldrb r3, [r9, #MEMWAIT_GRCG] |
| |
ldrb r2, egcwrd_egc |
| |
tst r0, #1 |
| |
CPUWORK r3 |
| |
beq egc_readword |
| |
ldrh r12, [r2, #EGC_SFT] |
| |
tst r12, #&1000 |
| |
bne egcwrd_std |
| |
add r2, r0, #1 |
| |
mov r3, r1 lsr #8 |
| |
stmdb sp!, {r2, r3, lr} |
| |
bl egc_writebyte |
| |
ldmia sp!, {r0, r1, lr} |
| |
b egc_writebyte |
| |
egcwrd_std stmdb sp!, {r0, r1, lr} |
| |
add r0, r0, #1 |
| |
mov r1, r1 lsr #8 |
| |
bl egc_writebyte |
| |
ldmia sp!, {r0, r1, lr} |
| |
b egc_writebyte |
| |
egcwrd_egc dcd egc |
| |
|
| |
|
| egc_wt ldrb r3, [r9, #MEMWAIT_GRCG] |
egc_wt ldrb r3, [r9, #MEMWAIT_GRCG] |
| CPUWORK r3 |
CPUWORK r3 |
| b egc_write |
b egc_writebyte |
| |
|
| egcw_wt |
|
| |
|
| |
egcw_wt ldrb r3, [r9, #MEMWAIT_GRCG] |
| |
ldrb r2, egcwwt_egc |
| |
tst r0, #1 |
| |
CPUWORK r3 |
| |
beq egc_writeword |
| |
ldrh r12, [r2, #EGC_SFT] |
| |
stmdb sp!, {r4, r5, lr} |
| |
tst r12, #&1000 |
| |
bne egcwwt_std |
| |
add r4, r0, #1 |
| |
mov r5, r1 lsr #8 |
| |
bl egc_readbyte |
| |
mov r1, r5 |
| |
mov r5, r0 |
| |
mov r0, r4 |
| |
bl egc_readbyte |
| |
orr r0, r5, r0 lsl #8 |
| |
ldmia sp!, {r4, r5, lr} |
| |
egcwwt_std mov r4, r0 |
| |
mov r5, r1 |
| |
add r0, r0, #1 |
| |
mov r1, r1 lsr #8 |
| |
bl egc_readbyte |
| |
mov r1, r5 |
| |
mov r5, r0 |
| |
mov r0, r4 |
| |
bl egc_readbyte |
| |
orr r0, r5, r0 lsl #8 |
| |
ldmia sp!, {r4, r5, lr} |
| |
egcwwt_egc dcd egc |
| |
|
| |
|
| ; ---- emmc |
; ---- emmc |
| |
|
| emmc_rd ldr r2, emrd_extmempp |
emmc_rd add r2, r9, #CPU_EMS |
| and r3, r0, #(3 << 14) |
and r3, r0, #(3 << 14) |
| ldr r2, [r2, r3 lsr #(14 - 2)] |
ldr r2, [r2, r3 lsr #(14 - 2)] |
| mov r0, r0 lsl #(32 - 14) |
mov r0, r0 lsl #(32 - 14) |
| ldrb r0, [r2, r0 lsr #(32 - 14)] |
ldrb r0, [r2, r0 lsr #(32 - 14)] |
| mov pc, lr |
mov pc, lr |
| emrd_extmempp dcd extmem + EM_PAGEPTR |
|
| |
|
| |
emmc_wt add r2, r9, #CPU_EMS |
| emmc_wt ldr r2, emwt_extmempp |
|
| and r3, r0, #(3 << 14) |
and r3, r0, #(3 << 14) |
| ldr r2, [r2, r3 lsr #(14 - 2)] |
ldr r2, [r2, r3 lsr #(14 - 2)] |
| mov r0, r0 lsl #(32 - 14) |
mov r0, r0 lsl #(32 - 14) |
| strb r1, [r2, r0 lsr #(32 - 14)] |
strb r1, [r2, r0 lsr #(32 - 14)] |
| mov pc, lr |
mov pc, lr |
| emwt_extmempp dcd extmem + EM_PAGEPTR |
|
| |
|
| |
|
| emmcw_rd ldr r2, emwrd_extmempp |
emmcw_rd add r2, r9, #CPU_EMS |
| and r12, r0, #(3 << 14) |
and r12, r0, #(3 << 14) |
| mov r0, r0 lsl #(32 - 14) |
mov r0, r0 lsl #(32 - 14) |
| ldr r3, [r2, r12 lsr #(14 - 2)] |
ldr r3, [r2, r12 lsr #(14 - 2)] |
|
Line 958 emmcw_rd ldr r2, emwrd_extmempp
|
Line 1086 emmcw_rd ldr r2, emwrd_extmempp
|
| add r3, r3, r0 lsr #(32 - 14) |
add r3, r3, r0 lsr #(32 - 14) |
| ldrh r0, [r3] |
ldrh r0, [r3] |
| mov pc, lr |
mov pc, lr |
| emwrd_extmempp dcd extmem + EM_PAGEPTR |
|
| emmcw_rd_odd ldrb r1, [r3, r0 lsr #(32 - 14)] |
emmcw_rd_odd ldrb r1, [r3, r0 lsr #(32 - 14)] |
| adds r0, r0, #(1 << (32 - 14)) |
adds r0, r0, #(1 << (32 - 14)) |
| beq emmcw_rd_3fff |
beq emmcw_rd_3fff |
|
Line 972 emmcw_rd_3fff eor r12, r12, #(1 << 14)
|
Line 1099 emmcw_rd_3fff eor r12, r12, #(1 << 14)
|
| mov pc, lr |
mov pc, lr |
| |
|
| |
|
| |
emmcw_wt add r2, r9, #CPU_EMS |
| |
|
| emmcw_wt ldr r2, emwwt_extmempp |
|
| and r12, r0, #(3 << 14) |
and r12, r0, #(3 << 14) |
| mov r0, r0 lsl #(32 - 14) |
mov r0, r0 lsl #(32 - 14) |
| ldr r3, [r2, r12 lsr #(14 - 2)] |
ldr r3, [r2, r12 lsr #(14 - 2)] |
|
Line 983 emmcw_wt ldr r2, emwwt_extmempp
|
Line 1108 emmcw_wt ldr r2, emwwt_extmempp
|
| add r3, r3, r0 lsr #(32 - 14) |
add r3, r3, r0 lsr #(32 - 14) |
| strh r1, [r3] |
strh r1, [r3] |
| mov pc, lr |
mov pc, lr |
| emwwt_extmempp dcd extmem + EM_PAGEPTR |
|
| emmcw_wt_odd strb r1, [r3, r0 lsr #(32 - 14)] |
emmcw_wt_odd strb r1, [r3, r0 lsr #(32 - 14)] |
| mov r1, r1 lsr #8 |
mov r1, r1 lsr #8 |
| adds r0, r0, #(1 << (32 - 14)) |
adds r0, r0, #(1 << (32 - 14)) |
|
Line 998 emmcw_wt_3fff eor r12, r12, #(1 << 14)
|
Line 1122 emmcw_wt_3fff eor r12, r12, #(1 << 14)
|
| |
|
| ; ---- itf |
; ---- itf |
| |
|
| i286_itf ldrb r2, [r9, #CPU_ITFBANK] |
i286_rb ldrb r2, [r9, #CPU_ITFBANK] |
| mov r3, r0 lsl #(32 - 15) |
orr r12, r0, #VRAM_STEP |
| add r12, r9, #ITF_ADRS |
cmp r2, #0 |
| |
ldreqb r0, [r0, r9] |
| |
ldrneb r0, [r12, r9] |
| |
mov pc, lr |
| |
|
| |
|
| |
i286_wb ldrb r2, [r9, #CPU_ITFBANK] |
| |
orr r12, r0, #(&1c8000 - &0e8000) |
| cmp r2, #0 |
cmp r2, #0 |
| ldreqb r0, [r9, r0] |
streqb r1, [r0, r9] |
| ldrneb r0, [r12, r3 lsr #(32 - 15)] |
strneb r1, [r12, r9] |
| mov pc, lr |
mov pc, lr |
| |
|
| |
|
| i286w_itf ldrb r2, [r9, #CPU_ITFBANK] |
i286w_rb ldrb r2, [r9, #CPU_ITFBANK] |
| tst r0, #1 |
tst r0, #1 |
| bne i286w_itf_odd |
bne i286w_rb_odd |
| cmp r2, #0 |
cmp r2, #0 |
| orrne r0, r0, #VRAM_STEP |
orrne r0, r0, #VRAM_STEP |
| ldrh r0, [r0, r9] |
ldrh r0, [r0, r9] |
| mov pc, lr |
mov pc, lr |
| i286w_itf_odd cmp r2, #0 |
i286w_rb_odd cmp r2, #0 |
| orrne r0, r0, #VRAM_STEP |
orrne r0, r0, #VRAM_STEP |
| add r2, r0, #1 |
add r2, r0, #1 |
| ldrb r0, [r0, r9] |
ldrb r0, [r0, r9] |
|
Line 1023 i286w_itf_odd cmp r2, #0
|
Line 1154 i286w_itf_odd cmp r2, #0
|
| mov pc, lr |
mov pc, lr |
| |
|
| |
|
| |
i286w_wb ldrb r2, [r9, #CPU_ITFBANK] |
| |
tst r0, #1 |
| |
bne i286w_wb_odd |
| |
cmp r2, #0 |
| |
addne r0, r0, #(&1c8000 - &0e8000) |
| |
strh r1, [r0, r9] |
| |
mov pc, lr |
| |
i286w_wb_odd cmp r2, #0 |
| |
addne r0, r0, #(&1c8000 - &0e8000) |
| |
mov r3, r1 lsr #8 |
| |
add r2, r0, #1 |
| |
strb r1, [r0, r9] |
| |
strb r3, [r2, r9] |
| |
mov pc, lr |
| |
|
| |
|
| |
|
| ; ---- other |
; ---- other |
| |
|
| |
i286_nonram_rw orr r0, r0, #&ff00 |
| i286_nonram_r mov r0, #&ff |
i286_nonram_r mov r0, #&ff |
| |
i286w_wn |
| i286_wn mov pc, lr |
i286_wn mov pc, lr |
| |
|
| i286_nonram_rw mov r0, #&ff |
|
| orr r0, r0, #&ff00 |
|
| i286w_wn mov pc, lr |
|
| |
|
| |
; ---- dispatch |
| |
|
| |
i286_memorymap |
| |
ldr r3, i2mm_memfn |
| |
and r1, r0, #1 |
| |
adr r2, mmaptbl |
| |
add r12, r2, r1 lsl #5 |
| |
ldr r1, [r2, r1 lsl #5] |
| |
ldr r2, [r12, #4] |
| |
str r1, [r3, #((0 * 32) + (0xe8000 >> (15 - 2)))] |
| |
str r1, [r3, #((0 * 32) + (0xf0000 >> (15 - 2)))] |
| |
str r2, [r3, #((0 * 32) + (0xf8000 >> (15 - 2)))] |
| |
ldr r1, [r12, #8] |
| |
ldr r2, [r12, #12] |
| |
str r1, [r3, #((4 * 32) + (0xd0000 >> (15 - 2)))] |
| |
str r1, [r3, #((4 * 32) + (0xd8000 >> (15 - 2)))] |
| |
str r2, [r3, #((4 * 32) + (0xe8000 >> (15 - 2)))] |
| |
str r2, [r3, #((4 * 32) + (0xf0000 >> (15 - 2)))] |
| |
str r2, [r3, #((4 * 32) + (0xf8000 >> (15 - 2)))] |
| |
ldr r1, [r12, #16] |
| |
ldr r2, [r12, #20] |
| |
str r1, [r3, #((8 * 32) + (0xe8000 >> (15 - 2)))] |
| |
str r1, [r3, #((8 * 32) + (0xf0000 >> (15 - 2)))] |
| |
str r2, [r3, #((8 * 32) + (0xf8000 >> (15 - 2)))] |
| |
ldr r1, [r12, #24] |
| |
ldr r2, [r12, #28] |
| |
str r1, [r3, #((12 * 32) + (0xd0000 >> (15 - 2)))] |
| |
str r1, [r3, #((12 * 32) + (0xd8000 >> (15 - 2)))] |
| |
str r2, [r3, #((12 * 32) + (0xe8000 >> (15 - 2)))] |
| |
str r2, [r3, #((12 * 32) + (0xf0000 >> (15 - 2)))] |
| |
str r2, [r3, #((12 * 32) + (0xf8000 >> (15 - 2)))] |
| |
mov pc, lr |
| |
i2mm_memfn dcd memfn |
| |
mmaptbl dcd i286_rd ; NEC |
| |
dcd i286_rb |
| |
dcd i286_wn |
| |
dcd i286_wn |
| |
dcd i286w_rd |
| |
dcd i286w_rb |
| |
dcd i286_wn |
| |
dcd i286_wn |
| |
dcd i286_rb ; EPSON |
| |
dcd i286_rb |
| |
dcd i286_wt |
| |
dcd i286_wb |
| |
dcd i286w_rb |
| |
dcd i286w_rb |
| |
dcd i286w_wt |
| |
dcd i286w_wb |
| |
|
| |
|
| |
i286_vram_dispatch |
| |
ldr r3, i2vd_memfn |
| |
and r1, r0, #15 |
| |
adr r2, vacctbl |
| |
add r2, r2, r1 lsl #4 |
| |
ldr r1, [r2] |
| |
ldr r12, [r2, #4] |
| |
tst r0, #&10 |
| |
str r1, [r3, #((0 * 32) + (0xa8000 >> (15 - 2)))] |
| |
str r1, [r3, #((0 * 32) + (0xb0000 >> (15 - 2)))] |
| |
str r1, [r3, #((0 * 32) + (0xb8000 >> (15 - 2)))] |
| |
strne r1, [r3, #((0 * 32) + (0xe0000 >> (15 - 2)))] |
| |
str r12, [r3, #((4 * 32) + (0xa8000 >> (15 - 2)))] |
| |
ldr r1, [r2, #8] |
| |
str r12, [r3, #((4 * 32) + (0xb0000 >> (15 - 2)))] |
| |
str r12, [r3, #((4 * 32) + (0xb8000 >> (15 - 2)))] |
| |
strne r12, [r3, #((4 * 32) + (0xe0000 >> (15 - 2)))] |
| |
str r1, [r3, #((8 * 32) + (0xa8000 >> (15 - 2)))] |
| |
ldr r12, [r2, #12] |
| |
str r1, [r3, #((8 * 32) + (0xb0000 >> (15 - 2)))] |
| |
str r1, [r3, #((8 * 32) + (0xb8000 >> (15 - 2)))] |
| |
strne r1, [r3, #((8 * 32) + (0xe0000 >> (15 - 2)))] |
| |
str r12, [r3, #((12 * 32) + (0xa8000 >> (15 - 2)))] |
| |
str r12, [r3, #((12 * 32) + (0xb0000 >> (15 - 2)))] |
| |
str r12, [r3, #((12 * 32) + (0xb8000 >> (15 - 2)))] |
| |
strne r12, [r3, #((12 * 32) + (0xe0000 >> (15 - 2)))] |
| |
movne pc, lr |
| |
|
| |
adr r1, i286_nonram_r |
| |
str r1, [r3, #((0 * 32) + (0xe0000 >> (15 - 2)))] |
| |
adr r1, i286_wn |
| |
str r1, [r3, #((4 * 32) + (0xe0000 >> (15 - 2)))] |
| |
adr r1, i286_nonram_rw |
| |
str r1, [r3, #((8 * 32) + (0xe0000 >> (15 - 2)))] |
| |
adr r1, i286_wn |
| |
str r1, [r3, #((12 * 32) + (0xe0000 >> (15 - 2)))] |
| |
mov pc, lr |
| |
|
| |
i2vd_memfn dcd memfn |
| |
vacctbl dcd vram_r0 ; 00 |
| |
dcd vram_w0 |
| |
dcd vramw_r0 |
| |
dcd vramw_w0 |
| |
dcd vram_r1 ; 10 |
| |
dcd vram_w1 |
| |
dcd vramw_r1 |
| |
dcd vramw_w1 |
| |
dcd vram_r0 ; 20 |
| |
dcd vram_w0 |
| |
dcd vramw_r0 |
| |
dcd vramw_w0 |
| |
dcd vram_r1 ; 30 |
| |
dcd vram_w1 |
| |
dcd vramw_r1 |
| |
dcd vramw_w1 |
| |
dcd vram_r0 ; 40 |
| |
dcd vram_w0 |
| |
dcd vramw_r0 |
| |
dcd vramw_w0 |
| |
dcd vram_r1 ; 50 |
| |
dcd vram_w1 |
| |
dcd vramw_r1 |
| |
dcd vramw_w1 |
| |
dcd vram_r0 ; 60 |
| |
dcd vram_w0 |
| |
dcd vramw_r0 |
| |
dcd vramw_w0 |
| |
dcd vram_r1 ; 70 |
| |
dcd vram_w1 |
| |
dcd vramw_r1 |
| |
dcd vramw_w1 |
| |
dcd grcg_tcr0 ; 80 |
| |
dcd grcg_tdw0 |
| |
dcd grcgw_tcr0 |
| |
dcd grcgw_tdw0 |
| |
dcd grcg_tcr1 ; 90 |
| |
dcd grcg_tdw1 |
| |
dcd grcgw_tcr1 |
| |
dcd grcgw_tdw1 |
| |
dcd egc_rd ; a0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
dcd egc_rd ; b0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
dcd vram_r0 ; c0 |
| |
dcd grcg_rmw0 |
| |
dcd vramw_r0 |
| |
dcd grcgw_rmw0 |
| |
dcd vram_r1 ; d0 |
| |
dcd grcg_rmw1 |
| |
dcd vramw_r1 |
| |
dcd grcgw_rmw1 |
| |
dcd egc_rd ; e0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
dcd egc_rd ; f0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
|
| END |
END |
| |
|
![[BACK]](/cvs/cvsweb/icons/back.gif){kind=icon}
Return to memorya.s CVS log ![[TXT]](/cvs/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvs/cvsweb/icons/dir.gif){kind=icon}
Up to [RetroPC.NET] / np2 / i286a