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version 1.6, 2003/12/20 10:27:55
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version 1.9, 2003/12/28 08:05:19
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Line 3
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Line 3
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| INCLUDE i286amem.inc |
INCLUDE i286amem.inc |
| INCLUDE i286aio.inc |
INCLUDE i286aio.inc |
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| IMPORT memfn |
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| IMPORT vramupdate |
IMPORT vramupdate |
| IMPORT tramupdate |
IMPORT tramupdate |
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Line 12
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Line 11
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| IMPORT egc_write_w |
IMPORT egc_write_w |
| IMPORT egc_read_w |
IMPORT egc_read_w |
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| EXPORT i286_rd |
EXPORT memfn |
| EXPORT i286_rdex |
EXPORT i286_memorymap |
| EXPORT i286w_rd |
EXPORT i286_vram_dispatch |
| EXPORT i286w_rdex |
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| EXPORT i286_wt |
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| EXPORT i286_wtex |
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| EXPORT i286w_wt |
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| EXPORT i286w_wtex |
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| EXPORT tram_rd |
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| EXPORT tramw_rd |
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| EXPORT tram_wt |
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| EXPORT tramw_wt |
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| EXPORT vram_r0 |
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| EXPORT vram_r1 |
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| EXPORT vramw_r0 |
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| EXPORT vramw_r1 |
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| EXPORT vram_w0 |
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| EXPORT vram_w1 |
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| EXPORT vramw_w0 |
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| EXPORT vramw_w1 |
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| EXPORT grcg_tcr0 |
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| EXPORT grcg_tcr1 |
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| EXPORT grcgw_tcr0 |
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| EXPORT grcgw_tcr1 |
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| EXPORT grcg_tdw0 |
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| EXPORT grcg_tdw1 |
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| EXPORT grcgw_tdw0 |
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| EXPORT grcgw_tdw1 |
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| EXPORT grcg_rmw0 |
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| EXPORT grcg_rmw1 |
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| EXPORT grcgw_rmw0 |
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| EXPORT grcgw_rmw1 |
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| ;; EXPORT egc_rd |
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| ;; EXPORT egcw_rd |
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| ;; EXPORT egc_wt |
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| ;; EXPORT egcw_wt |
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| EXPORT emmc_rd |
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| EXPORT emmcw_rd |
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| EXPORT emmc_wt |
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| EXPORT emmcw_wt |
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| EXPORT i286_itf |
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| EXPORT i286w_itf |
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| EXPORT i286_wn |
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| EXPORT i286w_wn |
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| EXPORT i286_nonram_r |
EXPORT i286_nonram_r |
| EXPORT i286_nonram_rw |
EXPORT i286_nonram_rw |
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AREA .data, DATA, READWRITE |
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memfn dcd i286_rdex ; 00 |
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dcd i286_rdex |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd ; 20 |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd ; 40 |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd ; 60 |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd ; 80 |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rd |
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dcd tram_rd ; a0 |
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dcd vram_r0 |
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dcd vram_r0 |
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dcd vram_r0 |
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dcd emmc_rd ; c0 |
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dcd emmc_rd |
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dcd i286_rd |
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dcd i286_rd |
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dcd vram_r0 ; e0 |
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dcd i286_rd |
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dcd i286_rd |
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dcd i286_rb |
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dcd i286_wtex ; 00 |
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dcd i286_wtex |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt ; 20 |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt ; 40 |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt ; 60 |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt ; 80 |
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dcd i286_wt |
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dcd i286_wt |
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dcd i286_wt |
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dcd tram_wt ; a0 |
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dcd vram_w0 |
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dcd vram_w0 |
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dcd vram_w0 |
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dcd emmc_wt ; c0 |
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dcd emmc_wt |
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dcd i286_wn |
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dcd i286_wn |
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dcd vram_w0 ; e0 |
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dcd i286_wn |
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dcd i286_wn |
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dcd i286_wn |
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dcd i286w_rdex ; 00 |
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dcd i286w_rdex |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd ; 20 |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd ; 40 |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd ; 60 |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd ; 80 |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd tramw_rd ; a0 |
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dcd vramw_r0 |
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dcd vramw_r0 |
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dcd vramw_r0 |
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dcd emmcw_rd ; c0 |
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dcd emmcw_rd |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd vramw_r0 ; e0 |
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dcd i286w_rd |
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dcd i286w_rd |
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dcd i286w_rb |
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dcd i286w_wtex ; 00 |
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dcd i286w_wtex |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt ; 20 |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt ; 40 |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt ; 60 |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt ; 80 |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd i286w_wt |
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dcd tramw_wt ; a0 |
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dcd vramw_w0 |
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dcd vramw_w0 |
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dcd vramw_w0 |
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dcd emmcw_wt ; c0 |
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dcd emmcw_wt |
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dcd i286w_wn |
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dcd i286w_wn |
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dcd vramw_w0 ; e0 |
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dcd i286w_wn |
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dcd i286w_wn |
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dcd i286w_wn |
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| AREA .text, CODE, READONLY |
AREA .text, CODE, READONLY |
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| ; ---- memory... |
; ---- memory... |
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Line 910 grcgw_clock ;; ldr r3, grww_vramop
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Line 994 grcgw_clock ;; ldr r3, grww_vramop
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| mov pc, lr |
mov pc, lr |
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| ; ---- egc |
; ---- egc |
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| egc_rd ldrb r3, [r9, #MEMWAIT_GRCG] |
egc_rd ldrb r3, [r9, #MEMWAIT_GRCG] |
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Line 918 egc_rd ldrb r3, [r9, #MEMWAIT_GRCG]
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Line 1001 egc_rd ldrb r3, [r9, #MEMWAIT_GRCG]
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| b egc_read |
b egc_read |
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| egcw_rd |
egcw_rd ldrb r3, [r9, #MEMWAIT_GRCG] |
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ldrb r2, egcwrd_egc |
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tst r0, #1 |
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CPUWORK r3 |
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beq egc_read_w |
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ldrh r12, [r2, #EGC_SFT] |
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tst r12, #&1000 |
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bne egcwrd_std |
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add r2, r0, #1 |
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mov r3, r1 lsr #8 |
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stmdb sp!, {r2, r3, lr} |
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bl egc_write |
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ldmia sp!, {r0, r1, lr} |
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b egc_write |
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egcwrd_std stmdb sp!, {r0, r1, lr} |
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add r0, r0, #1 |
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mov r1, r1 lsr #8 |
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bl egc_write |
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ldmia sp!, {r0, r1, lr} |
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b egc_write |
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egcwrd_egc dcd egc |
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| egc_wt ldrb r3, [r9, #MEMWAIT_GRCG] |
egc_wt ldrb r3, [r9, #MEMWAIT_GRCG] |
| CPUWORK r3 |
CPUWORK r3 |
| b egc_write |
b egc_write |
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| egcw_wt |
egcw_wt ldrb r3, [r9, #MEMWAIT_GRCG] |
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ldrb r2, egcwwt_egc |
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tst r0, #1 |
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CPUWORK r3 |
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beq egc_write_w |
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ldrh r12, [r2, #EGC_SFT] |
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stmdb sp!, {r4, r5, lr} |
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tst r12, #&1000 |
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bne egcwwt_std |
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add r4, r0, #1 |
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mov r5, r1 lsr #8 |
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bl egc_read |
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mov r1, r5 |
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mov r5, r0 |
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mov r0, r4 |
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bl egc_read |
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orr r0, r5, r0 lsl #8 |
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ldmia sp!, {r4, r5, lr} |
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egcwwt_std mov r4, r0 |
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mov r5, r1 |
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add r0, r0, #1 |
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mov r1, r1 lsr #8 |
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bl egc_read |
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mov r1, r5 |
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mov r5, r0 |
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mov r0, r4 |
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bl egc_read |
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orr r0, r5, r0 lsl #8 |
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ldmia sp!, {r4, r5, lr} |
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egcwwt_egc dcd egc |
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| ; ---- emmc |
; ---- emmc |
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Line 972 emmcw_rd_3fff eor r12, r12, #(1 << 14)
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Line 1103 emmcw_rd_3fff eor r12, r12, #(1 << 14)
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| mov pc, lr |
mov pc, lr |
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| emmcw_wt ldr r2, emwwt_extmempp |
emmcw_wt ldr r2, emwwt_extmempp |
| and r12, r0, #(3 << 14) |
and r12, r0, #(3 << 14) |
| mov r0, r0 lsl #(32 - 14) |
mov r0, r0 lsl #(32 - 14) |
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Line 998 emmcw_wt_3fff eor r12, r12, #(1 << 14)
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Line 1127 emmcw_wt_3fff eor r12, r12, #(1 << 14)
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| ; ---- itf |
; ---- itf |
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| i286_itf ldrb r2, [r9, #CPU_ITFBANK] |
i286_rb ldrb r2, [r9, #CPU_ITFBANK] |
| mov r3, r0 lsl #(32 - 15) |
orr r12, r0, #VRAM_STEP |
| add r12, r9, #ITF_ADRS |
cmp r2, #0 |
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ldreqb r0, [r0, r9] |
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ldrneb r0, [r12, r9] |
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mov pc, lr |
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i286_wb ldrb r2, [r9, #CPU_ITFBANK] |
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orr r12, r0, #(&1c8000 - &0e8000) |
| cmp r2, #0 |
cmp r2, #0 |
| ldreqb r0, [r9, r0] |
streqb r1, [r0, r9] |
| ldrneb r0, [r12, r3 lsr #(32 - 15)] |
strneb r1, [r12, r9] |
| mov pc, lr |
mov pc, lr |
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| i286w_itf ldrb r2, [r9, #CPU_ITFBANK] |
i286w_rb ldrb r2, [r9, #CPU_ITFBANK] |
| tst r0, #1 |
tst r0, #1 |
| bne i286w_itf_odd |
bne i286w_rb_odd |
| cmp r2, #0 |
cmp r2, #0 |
| orrne r0, r0, #VRAM_STEP |
orrne r0, r0, #VRAM_STEP |
| ldrh r0, [r0, r9] |
ldrh r0, [r0, r9] |
| mov pc, lr |
mov pc, lr |
| i286w_itf_odd cmp r2, #0 |
i286w_rb_odd cmp r2, #0 |
| orrne r0, r0, #VRAM_STEP |
orrne r0, r0, #VRAM_STEP |
| add r2, r0, #1 |
add r2, r0, #1 |
| ldrb r0, [r0, r9] |
ldrb r0, [r0, r9] |
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Line 1023 i286w_itf_odd cmp r2, #0
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Line 1159 i286w_itf_odd cmp r2, #0
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| mov pc, lr |
mov pc, lr |
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i286w_wb ldrb r2, [r9, #CPU_ITFBANK] |
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tst r0, #1 |
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bne i286w_wb_odd |
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cmp r2, #0 |
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addne r0, r0, #(&1c8000 - &0e8000) |
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strh r1, [r0, r9] |
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mov pc, lr |
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i286w_wb_odd cmp r2, #0 |
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addne r0, r0, #(&1c8000 - &0e8000) |
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mov r3, r1 lsr #8 |
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add r2, r0, #1 |
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strb r1, [r0, r9] |
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strb r3, [r2, r9] |
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mov pc, lr |
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| ; ---- other |
; ---- other |
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i286_nonram_rw orr r0, r0, #&ff00 |
| i286_nonram_r mov r0, #&ff |
i286_nonram_r mov r0, #&ff |
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i286w_wn |
| i286_wn mov pc, lr |
i286_wn mov pc, lr |
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| i286_nonram_rw mov r0, #&ff |
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| orr r0, r0, #&ff00 |
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| i286w_wn mov pc, lr |
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; ---- dispatch |
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i286_memorymap |
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ldr r3, i2mm_memfn |
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and r1, r0, #1 |
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adr r2, mmaptbl |
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add r12, r2, r1 lsl #5 |
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ldr r1, [r2, r1 lsl #5] |
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ldr r2, [r12, #4] |
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str r1, [r3, #((0 * 32) + (0xe8000 >> (15 - 2)))] |
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str r1, [r3, #((0 * 32) + (0xf0000 >> (15 - 2)))] |
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str r2, [r3, #((0 * 32) + (0xf8000 >> (15 - 2)))] |
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ldr r1, [r12, #8] |
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ldr r2, [r12, #12] |
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str r1, [r3, #((4 * 32) + (0xd0000 >> (15 - 2)))] |
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str r1, [r3, #((4 * 32) + (0xd8000 >> (15 - 2)))] |
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str r2, [r3, #((4 * 32) + (0xe8000 >> (15 - 2)))] |
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str r2, [r3, #((4 * 32) + (0xf0000 >> (15 - 2)))] |
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str r2, [r3, #((4 * 32) + (0xf8000 >> (15 - 2)))] |
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ldr r1, [r12, #16] |
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ldr r2, [r12, #20] |
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str r1, [r3, #((8 * 32) + (0xe8000 >> (15 - 2)))] |
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str r1, [r3, #((8 * 32) + (0xf0000 >> (15 - 2)))] |
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str r2, [r3, #((8 * 32) + (0xf8000 >> (15 - 2)))] |
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ldr r1, [r12, #24] |
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ldr r2, [r12, #28] |
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str r1, [r3, #((12 * 32) + (0xd0000 >> (15 - 2)))] |
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str r1, [r3, #((12 * 32) + (0xd8000 >> (15 - 2)))] |
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str r2, [r3, #((12 * 32) + (0xe8000 >> (15 - 2)))] |
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str r2, [r3, #((12 * 32) + (0xf0000 >> (15 - 2)))] |
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str r2, [r3, #((12 * 32) + (0xf8000 >> (15 - 2)))] |
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mov pc, lr |
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i2mm_memfn dcd memfn |
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mmaptbl dcd i286_rd ; NEC |
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dcd i286_rb |
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dcd i286_wn |
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dcd i286_wn |
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dcd i286w_rd |
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dcd i286w_rb |
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dcd i286_wn |
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dcd i286_wn |
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dcd i286_rb ; EPSON |
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dcd i286_rb |
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dcd i286_wt |
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dcd i286_wb |
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dcd i286w_rb |
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dcd i286w_rb |
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dcd i286w_wt |
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dcd i286w_wb |
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i286_vram_dispatch |
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ldr r3, i2vd_memfn |
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and r1, r0, #15 |
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adr r2, vacctbl |
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add r2, r2, r1 lsl #4 |
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ldr r1, [r2] |
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ldr r12, [r2, #4] |
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tst r0, #&10 |
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str r1, [r3, #((0 * 32) + (0xa8000 >> (15 - 2)))] |
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str r1, [r3, #((0 * 32) + (0xb0000 >> (15 - 2)))] |
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str r1, [r3, #((0 * 32) + (0xb8000 >> (15 - 2)))] |
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strne r1, [r3, #((0 * 32) + (0xe0000 >> (15 - 2)))] |
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str r12, [r3, #((4 * 32) + (0xa8000 >> (15 - 2)))] |
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ldr r1, [r2, #8] |
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str r12, [r3, #((4 * 32) + (0xb0000 >> (15 - 2)))] |
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str r12, [r3, #((4 * 32) + (0xb8000 >> (15 - 2)))] |
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strne r12, [r3, #((4 * 32) + (0xe0000 >> (15 - 2)))] |
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str r1, [r3, #((8 * 32) + (0xa8000 >> (15 - 2)))] |
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ldr r12, [r2, #12] |
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str r1, [r3, #((8 * 32) + (0xb0000 >> (15 - 2)))] |
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str r1, [r3, #((8 * 32) + (0xb8000 >> (15 - 2)))] |
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strne r1, [r3, #((8 * 32) + (0xe0000 >> (15 - 2)))] |
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str r12, [r3, #((12 * 32) + (0xa8000 >> (15 - 2)))] |
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str r12, [r3, #((12 * 32) + (0xb0000 >> (15 - 2)))] |
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str r12, [r3, #((12 * 32) + (0xb8000 >> (15 - 2)))] |
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strne r12, [r3, #((12 * 32) + (0xe0000 >> (15 - 2)))] |
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movne pc, lr |
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|
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adr r1, i286_nonram_r |
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str r1, [r3, #((0 * 32) + (0xe0000 >> (15 - 2)))] |
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adr r1, i286_wn |
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str r1, [r3, #((4 * 32) + (0xe0000 >> (15 - 2)))] |
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adr r1, i286_nonram_rw |
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str r1, [r3, #((8 * 32) + (0xe0000 >> (15 - 2)))] |
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adr r1, i286_wn |
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str r1, [r3, #((12 * 32) + (0xe0000 >> (15 - 2)))] |
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mov pc, lr |
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i2vd_memfn dcd memfn |
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vacctbl dcd vram_r0 ; 00 |
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dcd vram_w0 |
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dcd vramw_r0 |
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dcd vramw_w0 |
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dcd vram_r1 ; 10 |
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dcd vram_w1 |
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dcd vramw_r1 |
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dcd vramw_w1 |
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dcd vram_r0 ; 20 |
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dcd vram_w0 |
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dcd vramw_r0 |
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dcd vramw_w0 |
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dcd vram_r1 ; 30 |
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dcd vram_w1 |
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dcd vramw_r1 |
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dcd vramw_w1 |
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dcd vram_r0 ; 40 |
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dcd vram_w0 |
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dcd vramw_r0 |
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dcd vramw_w0 |
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dcd vram_r1 ; 50 |
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dcd vram_w1 |
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dcd vramw_r1 |
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dcd vramw_w1 |
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dcd vram_r0 ; 60 |
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dcd vram_w0 |
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dcd vramw_r0 |
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dcd vramw_w0 |
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dcd vram_r1 ; 70 |
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dcd vram_w1 |
| |
dcd vramw_r1 |
| |
dcd vramw_w1 |
| |
dcd grcg_tcr0 ; 80 |
| |
dcd grcg_tdw0 |
| |
dcd grcgw_tcr0 |
| |
dcd grcgw_tdw0 |
| |
dcd grcg_tcr1 ; 90 |
| |
dcd grcg_tdw1 |
| |
dcd grcgw_tcr1 |
| |
dcd grcgw_tdw1 |
| |
dcd egc_rd ; a0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
dcd egc_rd ; b0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
dcd vram_r0 ; c0 |
| |
dcd grcg_rmw0 |
| |
dcd vramw_r0 |
| |
dcd grcgw_rmw0 |
| |
dcd vram_r1 ; d0 |
| |
dcd grcg_rmw1 |
| |
dcd vramw_r1 |
| |
dcd grcgw_rmw1 |
| |
dcd egc_rd ; e0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
dcd egc_rd ; f0 |
| |
dcd egc_wt |
| |
dcd egcw_rd |
| |
dcd egcw_wt |
| |
|
| END |
END |
| |
|
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