| version 1.4, 2003/12/08 00:55:31 | version 1.6, 2004/01/05 09:31:25 | 
| Line 1 | Line 1 | 
 | #include        "compiler.h" | #include        "compiler.h" | 
| #include        "memory.h" | #include        "cpucore.h" | 
 | #include        "pccore.h" | #include        "pccore.h" | 
 | #include        "iocore.h" | #include        "iocore.h" | 
 | #include        "dmap.h" | #include        "dmap.h" | 
| Line 8 | Line 8 | 
 | void dmap_i286(void) { | void dmap_i286(void) { | 
 |  |  | 
 | DMACH   ch; | DMACH   ch; | 
| int             bit; | REG8    bit; | 
 |  |  | 
 | if (dmac.working) { | if (dmac.working) { | 
 | ch = dmac.dmach; | ch = dmac.dmach; | 
| Line 19  void dmap_i286(void) { | Line 19  void dmap_i286(void) { | 
 | if (!ch->leng.w) { | if (!ch->leng.w) { | 
 | dmac.stat |= bit; | dmac.stat |= bit; | 
 | dmac.working &= ~bit; | dmac.working &= ~bit; | 
| ch->extproc(DMAEXT_END); | ch->proc.extproc(DMAEXT_END); | 
 | } | } | 
 | ch->leng.w--; | ch->leng.w--; | 
 |  |  | 
 | switch(ch->mode & 0x0c) { | switch(ch->mode & 0x0c) { | 
 | case 0x00:              // verifty | case 0x00:              // verifty | 
| ch->inproc(); | ch->proc.inproc(); | 
 | break; | break; | 
 |  |  | 
 | case 0x04:              // port->mem | case 0x04:              // port->mem | 
| i286_memorywrite(ch->adrs.d, ch->inproc()); | i286_memorywrite(ch->adrs.d, ch->proc.inproc()); | 
 | break; | break; | 
 |  |  | 
 | default: | default: | 
| ch->outproc(i286_memoryread(ch->adrs.d)); | ch->proc.outproc(i286_memoryread(ch->adrs.d)); | 
 | break; | break; | 
 | } | } | 
 | ch->adrs.d += ((ch->mode & 0x20)?-1:1); | ch->adrs.d += ((ch->mode & 0x20)?-1:1); | 
| Line 47  void dmap_i286(void) { | Line 47  void dmap_i286(void) { | 
 | void dmap_v30(void) { | void dmap_v30(void) { | 
 |  |  | 
 | DMACH   ch; | DMACH   ch; | 
| int             bit; | REG8    bit; | 
 |  |  | 
 | if (dmac.working) { | if (dmac.working) { | 
 | ch = dmac.dmach; | ch = dmac.dmach; | 
| Line 58  void dmap_v30(void) { | Line 58  void dmap_v30(void) { | 
 | if (!ch->leng.w) { | if (!ch->leng.w) { | 
 | dmac.stat |= bit; | dmac.stat |= bit; | 
 | dmac.working &= ~bit; | dmac.working &= ~bit; | 
| ch->extproc(DMAEXT_END); | ch->proc.extproc(DMAEXT_END); | 
 | } | } | 
 | ch->leng.w--; | ch->leng.w--; | 
 |  |  | 
 | switch(ch->mode & 0x0c) { | switch(ch->mode & 0x0c) { | 
 | case 0x00:              // verifty | case 0x00:              // verifty | 
| ch->inproc(); | ch->proc.inproc(); | 
 | break; | break; | 
 |  |  | 
 | case 0x04:              // port->mem | case 0x04:              // port->mem | 
| i286_memorywrite(ch->adrs.d, ch->inproc()); | i286_memorywrite(ch->adrs.d, ch->proc.inproc()); | 
 | break; | break; | 
 |  |  | 
 | default: | default: | 
| ch->outproc(i286_memoryread(ch->adrs.d)); | ch->proc.outproc(i286_memoryread(ch->adrs.d)); | 
 | break; | break; | 
 | } | } | 
 | ch->adrs.w[DMA16_LOW] += ((ch->mode & 0x20)?-1:1); | ch->adrs.w[DMA16_LOW] += ((ch->mode & 0x20)?-1:1); |