--- np2/i286c/cpucore.h	2003/12/25 19:26:55	1.6
+++ np2/i286c/cpucore.h	2005/03/05 06:02:29	1.21
@@ -12,7 +12,7 @@
 #error : not support CPUCORE_IA32
 #endif
 
-#if !defined(CPUDEBUG)
+#if 1 // !defined(CPUDEBUG)
 enum {
 	I286_MEMREADMAX		= 0xa4000,
 	I286_MEMWRITEMAX	= 0xa0000
@@ -37,6 +37,13 @@ enum {
 };
 
 enum {
+	MSW_PE			= 0x0001,
+	MSW_MP			= 0x0002,
+	MSW_EM			= 0x0004,
+	MSW_TS			= 0x0008
+};
+
+enum {
 	CPUTYPE_V30		= 0x01
 };
 
@@ -141,33 +148,39 @@ typedef struct {
 		I286REG8	b;
 		I286REG16	w;
 	}		r;
-	SINT32	remainclock;
-	SINT32	baseclock;
-	UINT32	clock;
-	UINT32	adrsmask;						// ver0.72
 	UINT32	es_base;
 	UINT32	cs_base;
 	UINT32	ss_base;
 	UINT32	ds_base;
 	UINT32	ss_fix;
 	UINT32	ds_fix;
+	UINT32	adrsmask;						// ver0.72
 	UINT16	prefix;
 	UINT8	trap;
-	UINT8	cpu_type;
-	UINT32	____pf_semaphore;				// ج¤؛بحر
-	UINT32	____repbak;						// ج¤؛بحر
-	UINT32	inport;
+	UINT8	resetreq;						// ver0.72
 	UINT32	ovflag;
 	I286DTR	GDTR;
-	I286DTR	IDTR;
 	UINT16	MSW;
-	UINT8	resetreq;						// ver0.72
+	I286DTR	IDTR;
+	UINT16	LDTR;							// ver0.73
+	I286DTR	LDTRC;
+	UINT16	TR;
+	I286DTR	TRC;
+	UINT8	padding[2];
+
+	UINT8	cpu_type;
 	UINT8	itfbank;						// ver0.72
+	UINT16	ram_d0;
+	SINT32	remainclock;
+	SINT32	baseclock;
+	UINT32	clock;
 } I286STAT;
 
 typedef struct {							// for ver0.73
-	BYTE	*ext;
+	UINT8	*ext;
 	UINT32	extsize;
+	UINT8	*ems[4];
+	UINT32	inport;
 #if defined(CPUSTRUC_MEMWAIT)
 	UINT8	tramwait;
 	UINT8	vramwait;
@@ -190,8 +203,11 @@ extern	I286CORE	i286core;
 extern	const UINT8	iflags[];
 
 void i286c_initialize(void);
+void i286c_deinitialize(void);
 void i286c_reset(void);
 void i286c_shut(void);
+void i286c_setextsize(UINT32 size);
+void i286c_setemm(UINT frame, UINT32 addr);
 
 void CPUCALL i286c_interrupt(REG8 vect);
 
@@ -224,6 +240,16 @@ void v30c_step(void);
 #define	CPU_SS			i286core.s.r.w.ss
 #define	CPU_IP			i286core.s.r.w.ip
 
+#define	CPU_EAX			i286core.s.r.w.ax
+#define	CPU_EBX			i286core.s.r.w.bx
+#define	CPU_ECX			i286core.s.r.w.cx
+#define	CPU_EDX			i286core.s.r.w.dx
+#define	CPU_ESI			i286core.s.r.w.si
+#define	CPU_EDI			i286core.s.r.w.di
+#define	CPU_EBP			i286core.s.r.w.bp
+#define	CPU_ESP			i286core.s.r.w.sp
+#define	CPU_EIP			i286core.s.r.w.ip
+
 #define	ES_BASE			i286core.s.es_base
 #define	CS_BASE			i286core.s.cs_base
 #define	SS_BASE			i286core.s.ss_base
@@ -245,12 +271,15 @@ void v30c_step(void);
 #define	CPU_BASECLOCK	i286core.s.baseclock
 #define	CPU_CLOCK		i286core.s.clock
 #define	CPU_ADRSMASK	i286core.s.adrsmask
+#define	CPU_MSW			i286core.s.MSW
 #define	CPU_RESETREQ	i286core.s.resetreq
 #define	CPU_ITFBANK		i286core.s.itfbank
-#define	CPU_INPADRS		i286core.s.inport
+#define	CPU_RAM_D000	i286core.s.ram_d0
 
 #define	CPU_EXTMEM		i286core.e.ext
 #define	CPU_EXTMEMSIZE	i286core.e.extsize
+#define	CPU_INPADRS		i286core.e.inport
+#define	CPU_EMSPTR		i286core.e.ems
 
 #define	CPU_TYPE		i286core.s.cpu_type
 
@@ -267,12 +296,18 @@ void v30c_step(void);
 						i286core.s.trap = 0;
 #define	CPU_STI			i286core.s.r.w.flag |= I_FLAG;						\
 						i286core.s.trap = (i286core.s.r.w.flag >> 8) & 1;
+#define	CPU_A20EN(en)	CPU_ADRSMASK = (en)?0xfffffff:0x000fffff;
+
+#define	CPU_INITIALIZE				i286c_initialize
+#define	CPU_DEINITIALIZE			i286c_deinitialize
+#define	CPU_RESET					i286c_reset
+#define	CPU_CLEARPREFETCH()			
+#define	CPU_INTERRUPT(vect, soft)	i286c_interrupt(vect)
+#define	CPU_EXEC					i286c
+#define	CPU_EXECV30					v30c
+#define	CPU_SHUT					i286c_shut
+#define	CPU_SETEXTSIZE(size)		i286c_setextsize((UINT32)(size) << 20)
+#define	CPU_SETEMM(frame, addr)		i286c_setemm(frame, addr)
 
-#define	CPU_INITIALIZE		i286c_initialize
-#define	CPU_RESET			i286c_reset
-#define	CPU_CLEARPREFETCH()
-#define	CPU_INTERRUPT(v)	i286c_interrupt(v)
-#define	CPU_EXEC			i286c
-#define	CPU_EXECV30			v30c
-#define	CPU_SHUT			i286c_shut
+#define	CPU_STEPEXEC				i286c_step