--- np2/i286c/cpucore.h	2003/12/21 16:05:25	1.5
+++ np2/i286c/cpucore.h	2003/12/26 22:24:06	1.9
@@ -37,6 +37,13 @@ enum {
 };
 
 enum {
+	MSW_PE			= 0x0001,
+	MSW_MP			= 0x0002,
+	MSW_EM			= 0x0004,
+	MSW_TS			= 0x0008
+};
+
+enum {
 	CPUTYPE_V30		= 0x01
 };
 
@@ -159,8 +166,12 @@ typedef struct {
 	UINT32	inport;
 	UINT32	ovflag;
 	I286DTR	GDTR;
-	I286DTR	IDTR;
 	UINT16	MSW;
+	I286DTR	IDTR;
+	UINT16	LDTR;							// ver0.73
+	I286DTR	LDTRC;
+	UINT16	TR;
+	I286DTR	TRC;
 	UINT8	resetreq;						// ver0.72
 	UINT8	itfbank;						// ver0.72
 } I286STAT;
@@ -191,6 +202,7 @@ extern	const UINT8	iflags[];
 
 void i286c_initialize(void);
 void i286c_reset(void);
+void i286c_shut(void);
 
 void CPUCALL i286c_interrupt(REG8 vect);
 
@@ -244,6 +256,7 @@ void v30c_step(void);
 #define	CPU_BASECLOCK	i286core.s.baseclock
 #define	CPU_CLOCK		i286core.s.clock
 #define	CPU_ADRSMASK	i286core.s.adrsmask
+#define	CPU_MSW			i286core.s.MSW
 #define	CPU_RESETREQ	i286core.s.resetreq
 #define	CPU_ITFBANK		i286core.s.itfbank
 #define	CPU_INPADRS		i286core.s.inport
@@ -273,4 +286,5 @@ void v30c_step(void);
 #define	CPU_INTERRUPT(v)	i286c_interrupt(v)
 #define	CPU_EXEC			i286c
 #define	CPU_EXECV30			v30c
+#define	CPU_SHUT			i286c_shut