np2/i286x/v30patch.cpp - diff

Return to v30patch.cpp CVS log

Up to [RetroPC.NET] / np2 / i286x

Diff for /np2/i286x/v30patch.cpp between versions 1.4 and 1.12

version 1.4, 2003/12/01 10:45:46	version 1.12, 2005/03/26 07:53:48
Line 1	Line 1
#include "compiler.h"	#include "compiler.h"
#include "i286.h"	#include "cpucore.h"
#include "i286x.h"	#include "i286x.h"
#include "i286xadr.h"	#include "i286xadr.h"
#include "i286xs.h"	#include "i286xs.h"
#include "i286xrep.h"	#include "i286xrep.h"
#include "i286xcts.h"	#include "i286xcts.h"
#include "memory.h"
#include "pccore.h"	#include "pccore.h"
#include "bios.h"	#include "bios.h"
#include "iocore.h"	#include "iocore.h"
#include "i286x.mcr"	#include "i286x.mcr"
#include "i286xea.mcr"	#include "i286xea.mcr"
#include "dmap.h"	#include "dmax86.h"
	#if defined(ENABLE_TRAP)
	#include "steptrap.h"
	#endif


typedef struct {	typedef struct {
DWORD opnum;	UINT opnum;
void (*v30opcode)(void);	I286TBL v30opcode;
} V30PATCH_T;	} V30PATCH;

	static I286TBL v30op[256];
	static I286TBL v30op_repne[256];
	static I286TBL v30op_repe[256];
	static I286TBL v30ope0xf6_xtable[8];
	static I286TBL v30ope0xf7_xtable[8];


static const BYTE shiftbase16[256] =	static const UINT8 rotatebase16[256] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,	16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,	16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
Line 38 static const BYTE shiftbase16[256] =	Line 46 static const BYTE shiftbase16[256] =
16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,	16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15};	16, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15};

static const BYTE shiftbase09[256] =	static const UINT8 rotatebase09[256] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4, 5, 6,	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4, 5, 6,
7, 8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4,	7, 8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4,
5, 6, 7, 8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2,	5, 6, 7, 8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2,
Line 56 static const BYTE shiftbase09[256] =	Line 64 static const BYTE shiftbase09[256] =
8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4, 5,	8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4, 5,
6, 7, 8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3};	6, 7, 8, 9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3};

static const BYTE shiftbase17[256] =	static const UINT8 rotatebase17[256] =
{0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
16,17, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,	16,17, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,
15,16,17, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,	15,16,17, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,
Line 74 static const BYTE shiftbase17[256] =	Line 82 static const BYTE shiftbase17[256] =
3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17, 1,	3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17, 1,
2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17};	2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17};

	static const UINT8 shiftbase[256] =
	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
	16,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
	17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17};



I286 v30_reserved(void) {	I286 v30_reserved(void) {
Line 252 I286 v30_popf(void) { // 9D: popf	Line 278 I286 v30_popf(void) { // 9D: popf
I286 rol_r8_v30(void) {	I286 rol_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
rol byte ptr [edx], cl	rol byte ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
ret	ret
Line 262 I286 rol_r8_v30(void) {	Line 288 I286 rol_r8_v30(void) {
I286 ror_r8_v30(void) {	I286 ror_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
ror byte ptr [edx], cl	ror byte ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
ret	ret
Line 272 I286 ror_r8_v30(void) {	Line 298 I286 ror_r8_v30(void) {
I286 rcl_r8_v30(void) {	I286 rcl_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase09[ecx]	mov cl, rotatebase09[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcl byte ptr [edx], cl	rcl byte ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 283 I286 rcl_r8_v30(void) {	Line 309 I286 rcl_r8_v30(void) {
I286 rcr_r8_v30(void) {	I286 rcr_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase09[ecx]	mov cl, rotatebase09[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcr byte ptr [edx], cl	rcr byte ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 294 I286 rcr_r8_v30(void) {	Line 320 I286 rcr_r8_v30(void) {
I286 shl_r8_v30(void) {	I286 shl_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shl byte ptr [edx], cl	shl byte ptr [edx], cl
FLAG_STORE_OF	FLAG_STORE_OF
ret	ret
Line 304 I286 shl_r8_v30(void) {	Line 330 I286 shl_r8_v30(void) {
I286 shr_r8_v30(void) {	I286 shr_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shr byte ptr [edx], cl	shr byte ptr [edx], cl
FLAG_STORE_OF	FLAG_STORE_OF
ret	ret
Line 314 I286 shr_r8_v30(void) {	Line 340 I286 shr_r8_v30(void) {
I286 sar_r8_v30(void) {	I286 sar_r8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
sar byte ptr [edx], cl	sar byte ptr [edx], cl
FLAG_STORE0	FLAG_STORE0
ret	ret
Line 328 static void (*sftreg8v30_table[])(void)	Line 354 static void (*sftreg8v30_table[])(void)
I286 rol_ext8_v30(void) {	I286 rol_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
rol dl, cl	rol dl, cl
FLAG_STORE_OC	FLAG_STORE_OC
mov ecx, ebp	mov ecx, ebp
Line 339 I286 rol_ext8_v30(void) {	Line 365 I286 rol_ext8_v30(void) {
I286 ror_ext8_v30(void) {	I286 ror_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
ror dl, cl	ror dl, cl
FLAG_STORE_OC	FLAG_STORE_OC
mov ecx, ebp	mov ecx, ebp
Line 350 I286 ror_ext8_v30(void) {	Line 376 I286 ror_ext8_v30(void) {
I286 rcl_ext8_v30(void) {	I286 rcl_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase09[ecx]	mov cl, rotatebase09[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcl dl, cl	rcl dl, cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 362 I286 rcl_ext8_v30(void) {	Line 388 I286 rcl_ext8_v30(void) {
I286 rcr_ext8_v30(void) {	I286 rcr_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase09[ecx]	mov cl, rotatebase09[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcr dl, cl	rcr dl, cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 374 I286 rcr_ext8_v30(void) {	Line 400 I286 rcr_ext8_v30(void) {
I286 shl_ext8_v30(void) {	I286 shl_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shl dl, cl	shl dl, cl
FLAG_STORE_OF	FLAG_STORE_OF
mov ecx, ebp	mov ecx, ebp
Line 385 I286 shl_ext8_v30(void) {	Line 411 I286 shl_ext8_v30(void) {
I286 shr_ext8_v30(void) {	I286 shr_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shr dl, cl	shr dl, cl
FLAG_STORE_OF	FLAG_STORE_OF
mov ecx, ebp	mov ecx, ebp
Line 396 I286 shr_ext8_v30(void) {	Line 422 I286 shr_ext8_v30(void) {
I286 sar_ext8_v30(void) {	I286 sar_ext8_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
sar dl, cl	sar dl, cl
FLAG_STORE0	FLAG_STORE0
mov ecx, ebp	mov ecx, ebp
Line 460 I286 v30shift_ea8_data8(void) { // C	Line 486 I286 v30shift_ea8_data8(void) { // C
I286 rol_r16_v30(void) {	I286 rol_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
rol word ptr [edx], cl	rol word ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
ret	ret
Line 470 I286 rol_r16_v30(void) {	Line 496 I286 rol_r16_v30(void) {
I286 ror_r16_v30(void) {	I286 ror_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
ror word ptr [edx], cl	ror word ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
ret	ret
Line 480 I286 ror_r16_v30(void) {	Line 506 I286 ror_r16_v30(void) {
I286 rcl_r16_v30(void) {	I286 rcl_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase17[ecx]	mov cl, rotatebase17[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcl word ptr [edx], cl	rcl word ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 491 I286 rcl_r16_v30(void) {	Line 517 I286 rcl_r16_v30(void) {
I286 rcr_r16_v30(void) {	I286 rcr_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase17[ecx]	mov cl, rotatebase17[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcr word ptr [edx], cl	rcr word ptr [edx], cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 502 I286 rcr_r16_v30(void) {	Line 528 I286 rcr_r16_v30(void) {
I286 shl_r16_v30(void) {	I286 shl_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shl word ptr [edx], cl	shl word ptr [edx], cl
FLAG_STORE_OF	FLAG_STORE_OF
ret	ret
Line 512 I286 shl_r16_v30(void) {	Line 538 I286 shl_r16_v30(void) {
I286 shr_r16_v30(void) {	I286 shr_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shr word ptr [edx], cl	shr word ptr [edx], cl
FLAG_STORE_OF	FLAG_STORE_OF
ret	ret
Line 522 I286 shr_r16_v30(void) {	Line 548 I286 shr_r16_v30(void) {
I286 sar_r16_v30(void) {	I286 sar_r16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
sar word ptr [edx], cl	sar word ptr [edx], cl
FLAG_STORE0	FLAG_STORE0
ret	ret
Line 536 static void (*sftreg16v30_table[])(void)	Line 562 static void (*sftreg16v30_table[])(void)
I286 rol_ext16_v30(void) {	I286 rol_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
rol dx, cl	rol dx, cl
FLAG_STORE_OC	FLAG_STORE_OC
mov ecx, ebp	mov ecx, ebp
Line 547 I286 rol_ext16_v30(void) {	Line 573 I286 rol_ext16_v30(void) {
I286 ror_ext16_v30(void) {	I286 ror_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, rotatebase16[ecx]
ror dx, cl	ror dx, cl
FLAG_STORE_OC	FLAG_STORE_OC
mov ecx, ebp	mov ecx, ebp
Line 558 I286 ror_ext16_v30(void) {	Line 584 I286 ror_ext16_v30(void) {
I286 rcl_ext16_v30(void) {	I286 rcl_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase17[ecx]	mov cl, rotatebase17[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcl dx, cl	rcl dx, cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 570 I286 rcl_ext16_v30(void) {	Line 596 I286 rcl_ext16_v30(void) {
I286 rcr_ext16_v30(void) {	I286 rcr_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase17[ecx]	mov cl, rotatebase17[ecx]
CFLAG_LOAD	CFLAG_LOAD
rcr dx, cl	rcr dx, cl
FLAG_STORE_OC	FLAG_STORE_OC
Line 582 I286 rcr_ext16_v30(void) {	Line 608 I286 rcr_ext16_v30(void) {
I286 shl_ext16_v30(void) {	I286 shl_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shl dx, cl	shl dx, cl
FLAG_STORE_OF	FLAG_STORE_OF
mov ecx, ebp	mov ecx, ebp
Line 593 I286 shl_ext16_v30(void) {	Line 619 I286 shl_ext16_v30(void) {
I286 shr_ext16_v30(void) {	I286 shr_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
shr dx, cl	shr dx, cl
FLAG_STORE_OF	FLAG_STORE_OF
mov ecx, ebp	mov ecx, ebp
Line 604 I286 shr_ext16_v30(void) {	Line 630 I286 shr_ext16_v30(void) {
I286 sar_ext16_v30(void) {	I286 sar_ext16_v30(void) {

__asm {	__asm {
mov cl, shiftbase16[ecx]	mov cl, shiftbase[ecx]
sar dx, cl	sar dx, cl
FLAG_STORE0	FLAG_STORE0
mov ecx, ebp	mov ecx, ebp
Line 793 I286 v30_repe(void) { // F3: repe	Line 819 I286 v30_repe(void) { // F3: repe
}	}
}	}

	I286 v30div_ea8(void) { // F6-6: div ea8

	__asm {
	PREPART_EA8(14)
	movzx ebp, byte ptr I286_REG[eax]
	GET_NEXTPRE2
	jmp divcheck
	MEMORY_EA8(17)
	movzx ebp, byte ptr I286_MEM[ecx]
	jmp divcheck
	EXTMEM_EA8
	movzx ebp, al

	align 4
	divcheck: test ebp, ebp
	je divovf
	mov ax, I286_AX
	xor dx, dx
	div bp
	mov I286_AL, al
	mov I286_AH, dl
	mov dx, ax
	FLAG_STORE_OF
	test dh, dh
	jne divovf
	ret

	align 4
	divovf: INT_NUM(0)
	}
	}

	I286 v30idiv_ea8(void) { // F6-7 idiv ea8

	__asm {
	PREPART_EA8(17)
	movsx ebp, byte ptr I286_REG[eax]
	GET_NEXTPRE2
	jmp idivcheck
	MEMORY_EA8(20)
	movsx ebp, byte ptr I286_MEM[ecx]
	jmp idivcheck
	EXTMEM_EA8
	movsx ebp, al

	align 4
	idivcheck: test ebp, ebp
	je idivovf
	mov ax, I286_AX
	cwd
	idiv bp
	mov I286_AL, al
	mov I286_AH, dl
	mov dx, ax
	FLAG_STORE_OF
	bt dx, 7
	adc dh, 0
	jne idivovf
	ret

	align 4
	idivovf: INT_NUM(0)
	}
	}

	I286 v30_ope0xf6(void) { // F6:

	__asm {
	movzx eax, bh
	mov edi, eax
	shr edi, 3-2
	and edi, 7*4
	jmp v30ope0xf6_xtable[edi]
	}
	}

	I286 v30div_ea16(void) { // F7-6: div ea16

	__asm {
	PREPART_EA16(22)
	movzx ebp, word ptr I286_REG[eax*2]
	GET_NEXTPRE2
	jmp divcheck
	MEMORY_EA16(25)
	movzx ebp, word ptr I286_MEM[ecx]
	jmp divcheck
	EXTMEM_EA16
	movzx ebp, ax

	align 4
	divcheck: test ebp, ebp
	je divovf
	movzx eax, I286_DX
	shl eax, 16
	mov ax, I286_AX
	xor edx, edx
	div ebp
	mov I286_AX, ax
	mov I286_DX, dx
	FLAG_STORE_OF
	cmp eax, 10000h
	jae divovf
	ret

	align 4
	divovf: INT_NUM(0)
	}
	}

	I286 v30idiv_ea16(void) { // F7-7: idiv ea16

	__asm {
	PREPART_EA16(25)
	movsx ebp, word ptr I286_REG[eax*2]
	GET_NEXTPRE2
	jmp idivcheck
	MEMORY_EA16(28)
	movsx ebp, word ptr I286_MEM[ecx]
	jmp idivcheck
	EXTMEM_EA16
	cwde
	mov ebp, eax

static V30PATCH_T v30patch_op[] = {	align 4
	idivcheck: test ebp, ebp
	je idivovf
	movzx eax, I286_DX
	shl eax, 16
	mov ax, I286_AX
	cdq
	idiv ebp
	mov I286_AX, ax
	mov I286_DX, dx
	mov edx, eax
	FLAG_STORE_OF
	shr edx, 16
	adc dx, 0
	jne idivovf
	ret

	align 4
	idivovf: INT_NUM(0)
	}
	}

	I286 v30_ope0xf7(void) { // F7:

	__asm {
	movzx eax, bh
	mov edi, eax
	shr edi, 3-2
	and edi, 7*4
	jmp v30ope0xf7_xtable[edi]
	}
	}


	static const V30PATCH v30patch_op[] = {
{0x17, v30pop_ss}, // 17: pop ss	{0x17, v30pop_ss}, // 17: pop ss
{0x26, v30segprefix_es}, // 26: es:	{0x26, v30segprefix_es}, // 26: es:
{0x2e, v30segprefix_cs}, // 2E: cs:	{0x2e, v30segprefix_cs}, // 2E: cs:
Line 818 static V30PATCH_T v30patch_op[] = {	Line 1000 static V30PATCH_T v30patch_op[] = {
{0xd5, v30_aad}, // D5: AAD	{0xd5, v30_aad}, // D5: AAD
{0xd6, v30_xlat}, // D6: xlat (8086/V30)	{0xd6, v30_xlat}, // D6: xlat (8086/V30)
{0xf2, v30_repne}, // F2: repne	{0xf2, v30_repne}, // F2: repne
{0xf3, v30_repe} // F3: repe	{0xf3, v30_repe}, // F3: repe
};	{0xf6, v30_ope0xf6}, // F6:
	{0xf7, v30_ope0xf7}}; // F7:


// ----------------------------------------------------------------- repe	// ----------------------------------------------------------------- repe

Line 872 I286 v30repe_segprefix_ds(void) {	Line 1056 I286 v30repe_segprefix_ds(void) {
}	}


static V30PATCH_T v30patch_repe[] = {	static const V30PATCH v30patch_repe[] = {
{0x17, v30pop_ss}, // 17: pop ss	{0x17, v30pop_ss}, // 17: pop ss
{0x26, v30repe_segprefix_es}, // 26: repe es:	{0x26, v30repe_segprefix_es}, // 26: repe es:
{0x2e, v30repe_segprefix_cs}, // 2E: repe cs:	{0x2e, v30repe_segprefix_cs}, // 2E: repe cs:
Line 896 static V30PATCH_T v30patch_repe[] = {	Line 1080 static V30PATCH_T v30patch_repe[] = {
{0xd5, v30_aad}, // D5: AAD	{0xd5, v30_aad}, // D5: AAD
{0xd6, v30_xlat}, // D6: xlat (8086/V30)	{0xd6, v30_xlat}, // D6: xlat (8086/V30)
{0xf2, v30_repne}, // F2: repne	{0xf2, v30_repne}, // F2: repne
{0xf3, v30_repe} // F3: repe	{0xf3, v30_repe}, // F3: repe
};	{0xf6, v30_ope0xf6}, // F6:
	{0xf7, v30_ope0xf7}}; // F7:


// ----------------------------------------------------------------- repne	// ----------------------------------------------------------------- repne

Line 949 I286 v30repne_segprefix_ds(void) {	Line 1135 I286 v30repne_segprefix_ds(void) {
}	}
}	}

static V30PATCH_T v30patch_repne[] = {	static const V30PATCH v30patch_repne[] = {
{0x17, v30pop_ss}, // 17: pop ss	{0x17, v30pop_ss}, // 17: pop ss
{0x26, v30repne_segprefix_es}, // 26: repne es:	{0x26, v30repne_segprefix_es}, // 26: repne es:
{0x2e, v30repne_segprefix_cs}, // 2E: repne cs:	{0x2e, v30repne_segprefix_cs}, // 2E: repne cs:
Line 973 static V30PATCH_T v30patch_repne[] = {	Line 1159 static V30PATCH_T v30patch_repne[] = {
{0xd5, v30_aad}, // D5: AAD	{0xd5, v30_aad}, // D5: AAD
{0xd6, v30_xlat}, // D6: xlat (8086/V30)	{0xd6, v30_xlat}, // D6: xlat (8086/V30)
{0xf2, v30_repne}, // F2: repne	{0xf2, v30_repne}, // F2: repne
{0xf3, v30_repe} // F3: repe	{0xf3, v30_repe}, // F3: repe
};	{0xf6, v30_ope0xf6}, // F6:
	{0xf7, v30_ope0xf7}}; // F7:

// ---------------------------------------------------------------------------

void (*v30op[256])(void);	// ---------------------------------------------------------------------------
void (*v30op_repne[256])(void);
void (*v30op_repe[256])(void);

static void v30patching(void (dst[])(void), V30PATCH_T patch, int length) {	static void v30patching(I286TBL dst, const V30PATCH patch, int length) {

while(length--) {	while(length--) {
dst[patch->opnum] = patch->v30opcode;	dst[patch->opnum] = patch->v30opcode;
Line 990 static void v30patching(void (*dst[])(vo	Line 1174 static void v30patching(void (*dst[])(vo
}	}
}	}

#define V30PATCHING(a, b) v30patching(a, b, sizeof(b)/sizeof(V30PATCH_T))	#define V30PATCHING(a, b) v30patching(a, b, sizeof(b)/sizeof(V30PATCH))

void v30init(void) {	void v30xinit(void) {

CopyMemory(v30op, i286op, sizeof(v30op));	CopyMemory(v30op, i286op, sizeof(v30op));
V30PATCHING(v30op, v30patch_op);	V30PATCHING(v30op, v30patch_op);
Line 1000 void v30init(void) {	Line 1184 void v30init(void) {
V30PATCHING(v30op_repne, v30patch_repne);	V30PATCHING(v30op_repne, v30patch_repne);
CopyMemory(v30op_repe, i286op_repe, sizeof(v30op_repe));	CopyMemory(v30op_repe, i286op_repe, sizeof(v30op_repe));
V30PATCHING(v30op_repe, v30patch_repe);	V30PATCHING(v30op_repe, v30patch_repe);
	CopyMemory(v30ope0xf6_xtable, ope0xf6_xtable, sizeof(v30ope0xf6_xtable));
	v30ope0xf6_xtable[6] = v30div_ea8;
	v30ope0xf6_xtable[7] = v30idiv_ea8;
	CopyMemory(v30ope0xf7_xtable, ope0xf7_xtable, sizeof(v30ope0xf7_xtable));
	v30ope0xf7_xtable[6] = v30div_ea16;
	v30ope0xf7_xtable[7] = v30idiv_ea16;
}	}

LABEL void v30(void) {	LABEL void v30x(void) {

__asm {	__asm {
pushad	pushad
Line 1015 LABEL void v30(void) {	Line 1205 LABEL void v30(void) {
jne short v30_dma_mnlp	jne short v30_dma_mnlp

align 4	align 4
v30_mnlp: movzx eax, bl	v30_mnlp:
	#if defined(ENABLE_TRAP)
	mov edx, esi
	movzx ecx, I286_CS
	call steptrap
	#endif
	movzx eax, bl
call v30op[eax*4]	call v30op[eax*4]
cmp I286_REMCLOCK, 0	cmp I286_REMCLOCK, 0
jg v30_mnlp	jg v30_mnlp
Line 1025 v30_mnlp: movzx eax, bl	Line 1221 v30_mnlp: movzx eax, bl
ret	ret

align 4	align 4
v30_dma_mnlp: movzx eax, bl	v30_dma_mnlp:
	#if defined(ENABLE_TRAP)
	mov edx, esi
	movzx ecx, I286_CS
	call steptrap
	#endif
	movzx eax, bl
call v30op[eax*4]	call v30op[eax*4]
call dmap_i286	call dmax86
cmp I286_REMCLOCK, 0	cmp I286_REMCLOCK, 0
jg v30_dma_mnlp	jg v30_dma_mnlp
mov dword ptr (i286core.s.prefetchque), ebx	mov dword ptr (i286core.s.prefetchque), ebx
Line 1036 v30_dma_mnlp: movzx eax, bl	Line 1238 v30_dma_mnlp: movzx eax, bl
ret	ret

align 4	align 4
v30_trapping: movzx eax, bl	v30_trapping:
	#if defined(ENABLE_TRAP)
	mov edx, esi
	movzx ecx, I286_CS
	call steptrap
	#endif
	movzx eax, bl
call v30op[eax*4]	call v30op[eax*4]
cmp I286_TRAP, 0	cmp I286_TRAP, 0
je v30notrap	je v30notrap
Line 1049 v30notrap: mov dword ptr (i286core.s.p	Line 1257 v30notrap: mov dword ptr (i286core.s.p
}	}
}	}

LABEL void v30_step(void) {	LABEL void v30x_step(void) {

__asm {	__asm {
pushad	pushad
Line 1067 nexts:	Line 1275 nexts:
mov dword ptr (i286core.s.prefetchque), ebx	mov dword ptr (i286core.s.prefetchque), ebx
mov I286_IP, si	mov I286_IP, si

call dmap_i286	call dmax86
popad	popad
ret	ret
}	}

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.4
changed lines
	Added in v.1.12