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| version 1.23, 2005/03/03 06:59:41 | version 1.28, 2012/01/08 11:36:05 |
|---|---|
| Line 1 | Line 1 |
| /* $Id$ */ | |
| /* | /* |
| * Copyright (c) 2002-2003 NONAKA Kimihiro | * Copyright (c) 2002-2003 NONAKA Kimihiro |
| * All rights reserved. | * All rights reserved. |
| Line 12 | Line 10 |
| * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the | * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. | * documentation and/or other materials provided with the distribution. |
| * 3. The name of the author may not be used to endorse or promote products | |
| * derived from this software without specific prior written permission. | |
| * | * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| Line 58 int ctx_index = 0; | Line 54 int ctx_index = 0; |
| int cpu_inst_trace = 0; | int cpu_inst_trace = 0; |
| #endif | #endif |
| #if defined(DEBUG) | |
| int cpu_debug_rep_cont = 0; | |
| CPU_REGS cpu_debug_rep_regs; | |
| #endif | |
| void | void |
| exec_1step(void) | exec_1step(void) |
| Line 88 exec_1step(void) | Line 89 exec_1step(void) |
| buf[0] = '\0'; | buf[0] = '\0'; |
| for (i = 0; i < len; i++) { | for (i = 0; i < len; i++) { |
| snprintf(tmp, sizeof(tmp), "%02x ", d->opcode[i]); | snprintf(tmp, sizeof(tmp), "%02x ", d->opbyte[i]); |
| milstr_ncat(buf, tmp, sizeof(buf)); | milstr_ncat(buf, tmp, sizeof(buf)); |
| } | } |
| for (; i < 8; i++) { | for (; i < 8; i++) { |
| Line 98 exec_1step(void) | Line 99 exec_1step(void) |
| buf[0] = '\0'; | buf[0] = '\0'; |
| for (; i < d->nopbytes; i++) { | for (; i < d->nopbytes; i++) { |
| snprintf(tmp, sizeof(tmp), "%02x ", d->opcode[i]); | snprintf(tmp, sizeof(tmp), "%02x ", d->opbyte[i]); |
| milstr_ncat(buf, tmp, sizeof(buf)); | milstr_ncat(buf, tmp, sizeof(buf)); |
| if ((i % 8) == 7) { | if ((i % 8) == 7) { |
| VERBOSE((" : %s", buf)); | VERBOSE((" : %s", buf)); |
| Line 113 exec_1step(void) | Line 114 exec_1step(void) |
| ctx[ctx_index].opbytes = 0; | ctx[ctx_index].opbytes = 0; |
| #endif | #endif |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| if (CPU_STAT_BP && !(CPU_EFLAG & RF_FLAG)) { | |
| int i; | |
| for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | |
| if ((CPU_STAT_BP & (1 << i)) | |
| && (CPU_DR7_GET_RW(i) == CPU_DR7_RW_CODE) | |
| && (CPU_DR(i) == CPU_EIP) | |
| && (CPU_DR7_GET_LEN(i) == 0)) { | |
| CPU_DR6 |= CPU_DR6_B(i); | |
| EXCEPTION(DB_EXCEPTION, 0); | |
| } | |
| } | |
| } | |
| #endif /* IA32_SUPPORT_DEBUG_REGISTER */ | |
| for (prefix = 0; prefix < MAX_PREFIX; prefix++) { | for (prefix = 0; prefix < MAX_PREFIX; prefix++) { |
| GET_PCBYTE(op); | GET_PCBYTE(op); |
| #if defined(IA32_INSTRUCTION_TRACE) | #if defined(IA32_INSTRUCTION_TRACE) |
| Line 158 exec_1step(void) | Line 144 exec_1step(void) |
| /* normal / rep, but not use */ | /* normal / rep, but not use */ |
| if (!(insttable_info[op] & INST_STRING) || !CPU_INST_REPUSE) { | if (!(insttable_info[op] & INST_STRING) || !CPU_INST_REPUSE) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| goto check_break_point; | |
| #else | |
| return; | return; |
| #endif | |
| } | } |
| /* rep */ | /* rep */ |
| CPU_WORKCLOCK(5); | CPU_WORKCLOCK(5); |
| #if defined(DEBUG) | |
| if (!cpu_debug_rep_cont) { | |
| cpu_debug_rep_cont = 1; | |
| cpu_debug_rep_regs = CPU_STATSAVE.cpu_regs; | |
| } | |
| #endif | |
| if (!CPU_INST_AS32) { | if (!CPU_INST_AS32) { |
| if (CPU_CX != 0) { | if (CPU_CX != 0) { |
| if (!(insttable_info[op] & REP_CHECKZF)) { | if (!(insttable_info[op] & REP_CHECKZF)) { |
| /* rep */ | /* rep */ |
| for (;;) { | for (;;) { |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| if (--CPU_CX == 0) | if (--CPU_CX == 0) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| break; | break; |
| } | |
| if (CPU_REMCLOCK <= 0) { | if (CPU_REMCLOCK <= 0) { |
| CPU_EIP = CPU_PREV_EIP; | CPU_EIP = CPU_PREV_EIP; |
| break; | break; |
| Line 185 exec_1step(void) | Line 180 exec_1step(void) |
| /* repe */ | /* repe */ |
| for (;;) { | for (;;) { |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| if (--CPU_CX == 0 || CC_NZ) | if (--CPU_CX == 0 || CC_NZ) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| break; | break; |
| } | |
| if (CPU_REMCLOCK <= 0) { | if (CPU_REMCLOCK <= 0) { |
| CPU_EIP = CPU_PREV_EIP; | CPU_EIP = CPU_PREV_EIP; |
| break; | break; |
| Line 196 exec_1step(void) | Line 195 exec_1step(void) |
| /* repne */ | /* repne */ |
| for (;;) { | for (;;) { |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| if (--CPU_CX == 0 || CC_Z) | if (--CPU_CX == 0 || CC_Z) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| break; | break; |
| } | |
| if (CPU_REMCLOCK <= 0) { | if (CPU_REMCLOCK <= 0) { |
| CPU_EIP = CPU_PREV_EIP; | CPU_EIP = CPU_PREV_EIP; |
| break; | break; |
| Line 211 exec_1step(void) | Line 214 exec_1step(void) |
| /* rep */ | /* rep */ |
| for (;;) { | for (;;) { |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| if (--CPU_ECX == 0) | if (--CPU_ECX == 0) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| break; | break; |
| } | |
| if (CPU_REMCLOCK <= 0) { | if (CPU_REMCLOCK <= 0) { |
| CPU_EIP = CPU_PREV_EIP; | CPU_EIP = CPU_PREV_EIP; |
| break; | break; |
| Line 222 exec_1step(void) | Line 229 exec_1step(void) |
| /* repe */ | /* repe */ |
| for (;;) { | for (;;) { |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| if (--CPU_ECX == 0 || CC_NZ) | if (--CPU_ECX == 0 || CC_NZ) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| break; | break; |
| } | |
| if (CPU_REMCLOCK <= 0) { | if (CPU_REMCLOCK <= 0) { |
| CPU_EIP = CPU_PREV_EIP; | CPU_EIP = CPU_PREV_EIP; |
| break; | break; |
| Line 233 exec_1step(void) | Line 244 exec_1step(void) |
| /* repne */ | /* repne */ |
| for (;;) { | for (;;) { |
| (*insttable_1byte[CPU_INST_OP32][op])(); | (*insttable_1byte[CPU_INST_OP32][op])(); |
| if (--CPU_ECX == 0 || CC_Z) | if (--CPU_ECX == 0 || CC_Z) { |
| #if defined(DEBUG) | |
| cpu_debug_rep_cont = 0; | |
| #endif | |
| break; | break; |
| } | |
| if (CPU_REMCLOCK <= 0) { | if (CPU_REMCLOCK <= 0) { |
| CPU_EIP = CPU_PREV_EIP; | CPU_EIP = CPU_PREV_EIP; |
| break; | break; |
| Line 243 exec_1step(void) | Line 258 exec_1step(void) |
| } | } |
| } | } |
| } | } |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| check_break_point: | |
| if (CPU_TRAP || (CPU_STAT_BP_EVENT & ~CPU_STAT_BP_EVENT_RF)) { | |
| UINT8 orig = CPU_STAT_BP_EVENT & ~CPU_STAT_BP_EVENT_RF; | |
| CPU_STAT_BP_EVENT &= CPU_STAT_BP_EVENT_RF; | |
| CPU_DR6 |= (orig & 0xf); | |
| if (orig & CPU_STAT_BP_EVENT_TASK) { | |
| CPU_DR6 |= CPU_DR6_BT; | |
| } | |
| if (CPU_TRAP) { | |
| CPU_DR6 |= CPU_DR6_BS; | |
| } | |
| INTERRUPT(DB_EXCEPTION, TRUE, FALSE, 0); | |
| } | |
| if (CPU_EFLAG & RF_FLAG) { | |
| if (CPU_STAT_BP_EVENT & CPU_STAT_BP_EVENT_RF) { | |
| /* after IRETD or task switch */ | |
| CPU_STAT_BP_EVENT &= ~CPU_STAT_BP_EVENT_RF; | |
| } else { | |
| CPU_EFLAG &= ~RF_FLAG; | |
| } | |
| } | |
| #endif /* IA32_SUPPORT_DEBUG_REGISTER */ | |
| } | } |