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| version 1.14, 2004/02/05 16:43:44 | version 1.18, 2004/02/19 03:04:01 |
|---|---|
| Line 149 typedef struct { | Line 149 typedef struct { |
| typedef struct { | typedef struct { |
| descriptor_t sreg[CPU_SEGREG_NUM]; | descriptor_t sreg[CPU_SEGREG_NUM]; |
| descriptor_t ldtr_desc; | descriptor_t ldtr; |
| descriptor_t tr_desc; | descriptor_t tr; |
| UINT32 adrsmask; | UINT32 adrsmask; |
| DWORD ovflag; | DWORD ovflag; |
| Line 161 typedef struct { | Line 161 typedef struct { |
| BYTE page_wp; | BYTE page_wp; |
| BYTE user_mode; | |
| BYTE protected_mode; | BYTE protected_mode; |
| BYTE paging; | BYTE paging; |
| BYTE vm86; | BYTE vm86; |
| BYTE user_mode; | |
| BYTE hlt; | |
| BYTE pad[3]; | |
| DWORD pde_base; | DWORD pde_base; |
| Line 417 void set_eflags(DWORD new_flags, DWORD m | Line 420 void set_eflags(DWORD new_flags, DWORD m |
| #define CPU_STAT_SS32 CPU_STATSAVE.cpu_stat.ss_32 | #define CPU_STAT_SS32 CPU_STATSAVE.cpu_stat.ss_32 |
| #define CPU_STAT_RESETREQ CPU_STATSAVE.cpu_stat.resetreq | #define CPU_STAT_RESETREQ CPU_STATSAVE.cpu_stat.resetreq |
| #define CPU_STAT_PM CPU_STATSAVE.cpu_stat.protected_mode | #define CPU_STAT_PM CPU_STATSAVE.cpu_stat.protected_mode |
| #define CPU_STAT_VM86 CPU_STATSAVE.cpu_stat.vm86 | |
| #define CPU_STAT_PAGING CPU_STATSAVE.cpu_stat.paging | #define CPU_STAT_PAGING CPU_STATSAVE.cpu_stat.paging |
| #define CPU_STAT_VM86 CPU_STATSAVE.cpu_stat.vm86 | |
| #define CPU_STAT_WP CPU_STATSAVE.cpu_stat.page_wp | #define CPU_STAT_WP CPU_STATSAVE.cpu_stat.page_wp |
| #define CPU_STAT_CPL CPU_STAT_SREG(CPU_CS_INDEX).rpl | #define CPU_STAT_CPL CPU_STAT_SREG(CPU_CS_INDEX).rpl |
| #define CPU_STAT_USER_MODE CPU_STATSAVE.cpu_stat.user_mode | #define CPU_STAT_USER_MODE CPU_STATSAVE.cpu_stat.user_mode |
| #define CPU_STAT_PDE_BASE CPU_STATSAVE.cpu_stat.pde_base | #define CPU_STAT_PDE_BASE CPU_STATSAVE.cpu_stat.pde_base |
| #define CPU_STAT_HLT CPU_STATSAVE.cpu_stat.hlt | |
| #define CPU_STAT_IOPL ((CPU_EFLAG & IOPL_FLAG) >> 12) | #define CPU_STAT_IOPL ((CPU_EFLAG & IOPL_FLAG) >> 12) |
| #define CPU_IOPL0 0 | #define CPU_IOPL0 0 |
| #define CPU_IOPL1 1 | #define CPU_IOPL1 1 |
| Line 433 void set_eflags(DWORD new_flags, DWORD m | Line 438 void set_eflags(DWORD new_flags, DWORD m |
| #define CPU_STAT_IOADDR CPU_STATSAVE.cpu_stat.ioaddr | #define CPU_STAT_IOADDR CPU_STATSAVE.cpu_stat.ioaddr |
| #define CPU_STAT_IOLIMIT CPU_STATSAVE.cpu_stat.iolimit | #define CPU_STAT_IOLIMIT CPU_STATSAVE.cpu_stat.iolimit |
| #define CPU_STAT_NERROR CPU_STATSAVE.cpu_stat.nerror | #define CPU_STAT_PREV_EXCEPTION CPU_STATSAVE.cpu_stat.prev_exception |
| #define CPU_STAT_PREV_EXCEPTION CPU_STATSAVE.cpu_stat.prev_exception | #define CPU_STAT_EXCEPTION_COUNTER CPU_STATSAVE.cpu_stat.nerror |
| #define CPU_STAT_EXCEPTION_COUNTER_INC() CPU_STATSAVE.cpu_stat.nerror++ | |
| #define CPU_STAT_EXCEPTION_COUNTER_CLEAR() CPU_STATSAVE.cpu_stat.nerror = 0 | |
| #define CPU_MODE_SUPERVISER 0 | #define CPU_MODE_SUPERVISER 0 |
| #define CPU_MODE_USER 1 | #define CPU_MODE_USER 1 |
| #define CPU_SET_CPL(cpl) \ | #define CPU_SET_CPL(cpl) \ |
| do { \ | do { \ |
| BYTE __t = (cpl) & 3; \ | BYTE __t = (BYTE)((cpl) & 3); \ |
| CPU_STAT_CPL = __t; \ | CPU_STAT_CPL = __t; \ |
| CPU_STAT_USER_MODE = (__t == 3) ? CPU_MODE_USER : CPU_MODE_SUPERVISER; \ | CPU_STAT_USER_MODE = (__t == 3) ? CPU_MODE_USER : CPU_MODE_SUPERVISER; \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| Line 455 do { \ | Line 462 do { \ |
| #define CPU_IDTR_LIMIT CPU_STATSAVE.cpu_sysregs.idtr_limit | #define CPU_IDTR_LIMIT CPU_STATSAVE.cpu_sysregs.idtr_limit |
| #define CPU_IDTR_BASE CPU_STATSAVE.cpu_sysregs.idtr_base | #define CPU_IDTR_BASE CPU_STATSAVE.cpu_sysregs.idtr_base |
| #define CPU_LDTR CPU_STATSAVE.cpu_sysregs.ldtr | #define CPU_LDTR CPU_STATSAVE.cpu_sysregs.ldtr |
| #define CPU_LDTR_DESC CPU_STATSAVE.cpu_stat.ldtr_desc | #define CPU_LDTR_DESC CPU_STATSAVE.cpu_stat.ldtr |
| #define CPU_LDTR_BASE CPU_STATSAVE.cpu_stat.ldtr_desc.u.seg.segbase | #define CPU_LDTR_BASE CPU_STATSAVE.cpu_stat.ldtr.u.seg.segbase |
| #define CPU_LDTR_END CPU_STATSAVE.cpu_stat.ldtr_desc.u.seg.segend | #define CPU_LDTR_END CPU_STATSAVE.cpu_stat.ldtr.u.seg.segend |
| #define CPU_LDTR_LIMIT CPU_STATSAVE.cpu_stat.ldtr_desc.u.seg.limit | #define CPU_LDTR_LIMIT CPU_STATSAVE.cpu_stat.ldtr.u.seg.limit |
| #define CPU_TR CPU_STATSAVE.cpu_sysregs.tr | #define CPU_TR CPU_STATSAVE.cpu_sysregs.tr |
| #define CPU_TR_DESC CPU_STATSAVE.cpu_stat.tr_desc | #define CPU_TR_DESC CPU_STATSAVE.cpu_stat.tr |
| #define CPU_TR_BASE CPU_STATSAVE.cpu_stat.tr_desc.u.seg.segbase | #define CPU_TR_BASE CPU_STATSAVE.cpu_stat.tr.u.seg.segbase |
| #define CPU_TR_END CPU_STATSAVE.cpu_stat.tr_desc.u.seg.segend | #define CPU_TR_END CPU_STATSAVE.cpu_stat.tr.u.seg.segend |
| #define CPU_TR_LIMIT CPU_STATSAVE.cpu_stat.tr_desc.u.seg.limit | #define CPU_TR_LIMIT CPU_STATSAVE.cpu_stat.tr.u.seg.limit |
| /* | /* |
| * control register | * control register |
| Line 518 void ia32withtrap(void); | Line 525 void ia32withtrap(void); |
| void ia32withdma(void); | void ia32withdma(void); |
| void ia32_step(void); | void ia32_step(void); |
| void CPUCALL ia32_interrupt(BYTE vect); | void CPUCALL ia32_interrupt(REG8 vect); |
| void CPUCALL ia32_exception(DWORD vect, DWORD p1, DWORD p2); | void CPUCALL ia32_exception(DWORD vect, DWORD p1, DWORD p2); |
| void exec_1step(void); | void exec_1step(void); |
| Line 526 void exec_1step(void); | Line 533 void exec_1step(void); |
| #define INST_STRING (1 << 1) | #define INST_STRING (1 << 1) |
| #define REP_CHECKZF (1 << 7) | #define REP_CHECKZF (1 << 7) |
| int disasm(DWORD *eip, char *buf, size_t size); | |
| void ia32_printf(const char *buf, ...); | void ia32_printf(const char *buf, ...); |
| void ia32_warning(const char *buf, ...); | void ia32_warning(const char *buf, ...); |
| void ia32_panic(const char *buf, ...); | void ia32_panic(const char *buf, ...); |