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| version 1.27, 2004/03/24 14:34:23 | version 1.31, 2004/07/29 13:06:08 |
|---|---|
| Line 117 enum { | Line 117 enum { |
| MAX_PREFIX = 8 | MAX_PREFIX = 8 |
| }; | }; |
| enum { | |
| CPU_PREFETCH_QUEUE_LENGTH = 16 | |
| }; | |
| typedef struct { | typedef struct { |
| REG32 reg[CPU_REG_NUM]; | REG32 reg[CPU_REG_NUM]; |
| UINT16 sreg[CPU_SEGREG_NUM]; | UINT16 sreg[CPU_SEGREG_NUM]; |
| Line 157 typedef struct { | Line 153 typedef struct { |
| descriptor_t ldtr; | descriptor_t ldtr; |
| descriptor_t tr; | descriptor_t tr; |
| BYTE prefetch[CPU_PREFETCH_QUEUE_LENGTH]; | |
| SINT8 prefetch_remain; | |
| UINT8 pad2[3]; | |
| UINT32 adrsmask; | UINT32 adrsmask; |
| UINT32 ovflag; | UINT32 ovflag; |
| Line 213 typedef struct { | Line 205 typedef struct { |
| UINT32 clock; | UINT32 clock; |
| } I386STAT; | } I386STAT; |
| typedef struct { /* for ver0.73 */ | typedef struct { |
| BYTE *ext; | BYTE *ext; |
| UINT32 extsize; | UINT32 extsize; |
| UINT32 inport; | UINT32 inport; |
| BYTE *ems[4]; | |
| } I386EXT; | } I386EXT; |
| typedef struct { | typedef struct { |
| Line 243 extern I386CORE i386core; | Line 236 extern I386CORE i386core; |
| #define CPU_EXTMEM i386core.e.ext | #define CPU_EXTMEM i386core.e.ext |
| #define CPU_EXTMEMSIZE i386core.e.extsize | #define CPU_EXTMEMSIZE i386core.e.extsize |
| #define CPU_INPADRS i386core.e.inport | #define CPU_INPADRS i386core.e.inport |
| #define CPU_EMSPTR i386core.e.ems | |
| extern sigjmp_buf exec_1step_jmpbuf; | extern sigjmp_buf exec_1step_jmpbuf; |
| Line 454 void set_eflags(UINT32 new_flags, UINT32 | Line 448 void set_eflags(UINT32 new_flags, UINT32 |
| #define CPU_STAT_EXCEPTION_COUNTER_INC() CPU_STATSAVE.cpu_stat.nerror++ | #define CPU_STAT_EXCEPTION_COUNTER_INC() CPU_STATSAVE.cpu_stat.nerror++ |
| #define CPU_STAT_EXCEPTION_COUNTER_CLEAR() CPU_STATSAVE.cpu_stat.nerror = 0 | #define CPU_STAT_EXCEPTION_COUNTER_CLEAR() CPU_STATSAVE.cpu_stat.nerror = 0 |
| #define CPU_PREFETCHQ CPU_STATSAVE.cpu_stat.prefetch | |
| #define CPU_PREFETCHQ_REMAIN CPU_STATSAVE.cpu_stat.prefetch_remain | |
| #if defined(IA32_SUPPORT_PREFETCH_QUEUE) | |
| #define CPU_PREFETCH_CLEAR() CPU_PREFETCHQ_REMAIN = 0 | |
| #else /* !IA32_SUPPORT_PREFETCH_QUEUE */ | |
| #define CPU_PREFETCH_CLEAR() | #define CPU_PREFETCH_CLEAR() |
| #endif /* IA32_SUPPORT_PREFETCH_QUEUE */ | #define CPU_PREFETCHQ_REMAIN_ADD(d) |
| #define CPU_PREFETCHQ_REMAIN_SUB(d) | |
| #define CPU_MODE_SUPERVISER 0 | #define CPU_MODE_SUPERVISER 0 |
| #define CPU_MODE_USER (1 << 3) | #define CPU_MODE_USER (1 << 3) |
| Line 580 do { \ | Line 569 do { \ |
| void ia32_init(void); | void ia32_init(void); |
| void ia32_initreg(void); | void ia32_initreg(void); |
| void ia32_setextsize(UINT32 size); | void ia32_setextsize(UINT32 size); |
| void ia32_setemm(UINT frame, UINT32 addr); | |
| void ia32reset(void); | void ia32reset(void); |
| void ia32shut(void); | void ia32shut(void); |
| void ia32a20enable(BOOL enable); | |
| void ia32(void); | void ia32(void); |
| void ia32_step(void); | void ia32_step(void); |
| void CPUCALL ia32_interrupt(int vect, int soft); | void CPUCALL ia32_interrupt(int vect, int soft); |
| Line 629 void dbg_printf(const char *str, ...); | Line 620 void dbg_printf(const char *str, ...); |
| /* | /* |
| * Misc. | * Misc. |
| */ | */ |
| void memory_dump(int idx, UINT32 madr); | |
| void gdtr_dump(UINT32 base, UINT limit); | void gdtr_dump(UINT32 base, UINT limit); |
| void idtr_dump(UINT32 base, UINT limit); | void idtr_dump(UINT32 base, UINT limit); |
| void ldtr_dump(UINT32 base, UINT limit); | void ldtr_dump(UINT32 base, UINT limit); |
| void tr_dump(UINT16 selector, UINT32 base, UINT limit); | void tr_dump(UINT16 selector, UINT32 base, UINT limit); |
| UINT32 pde_dump(UINT32 base, int idx); | |
| UINT32 convert_laddr_to_paddr(UINT32 laddr); | |
| UINT32 convert_vaddr_to_paddr(unsigned int idx, UINT32 offset); | |
| /* | /* |
| * disasm | * disasm |