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| version 1.3, 2003/12/22 18:00:31 | version 1.10, 2004/01/23 16:32:36 |
|---|---|
| Line 110 enum { | Line 110 enum { |
| CPU_SEGREG_NUM | CPU_SEGREG_NUM |
| }; | }; |
| enum { | |
| CPU_TEST_REG_NUM = 8 | |
| }; | |
| enum { | |
| CPU_DEBUG_REG_NUM = 8 | |
| }; | |
| enum { | |
| MAX_PREFIX = 8 | |
| }; | |
| typedef struct { | typedef struct { |
| REG32 reg[CPU_REG_NUM]; | REG32 reg[CPU_REG_NUM]; |
| WORD sreg[CPU_SEGREG_NUM]; | WORD sreg[CPU_SEGREG_NUM]; |
| Line 118 typedef struct { | Line 130 typedef struct { |
| REG32 eip; | REG32 eip; |
| REG32 prev_eip; | REG32 prev_eip; |
| DWORD tr[CPU_TEST_REG_NUM]; | |
| DWORD dr[CPU_DEBUG_REG_NUM]; | |
| } CPU_REGS; | } CPU_REGS; |
| typedef struct { | typedef struct { |
| Line 142 typedef struct { | Line 157 typedef struct { |
| typedef struct { | typedef struct { |
| descriptor_t sreg[CPU_SEGREG_NUM]; | descriptor_t sreg[CPU_SEGREG_NUM]; |
| DWORD inport; | UINT32 adrsmask; |
| DWORD ovflag; | DWORD ovflag; |
| BYTE ss_32; | BYTE ss_32; |
| BYTE resetreq; | |
| BYTE trap; | BYTE trap; |
| BYTE cpu_type; | |
| BYTE _dummy; | BYTE _dummy; |
| BYTE cpl; | BYTE cpl; |
| Line 177 typedef struct { | Line 192 typedef struct { |
| CPU_INST cpu_inst; | CPU_INST cpu_inst; |
| CPU_INST cpu_inst_default; | CPU_INST cpu_inst_default; |
| /* protected by cpu shut */ | |
| UINT8 cpu_type; | |
| UINT8 itfbank; | |
| UINT16 ram_d0; | |
| SINT32 remainclock; | SINT32 remainclock; |
| SINT32 baseclock; | SINT32 baseclock; |
| UINT32 clock; | UINT32 clock; |
| UINT32 adrsmask; /* ? */ | |
| UINT32 inport; /* ? */ | |
| UINT8 resetreq; | |
| UINT8 itfbank; | |
| } I386STAT; | } I386STAT; |
| typedef struct { /* for ver0.73 */ | typedef struct { /* for ver0.73 */ |
| BYTE *ext; | BYTE *ext; |
| UINT32 extsize; | UINT32 extsize; |
| UINT32 inport; | |
| } I386EXT; | } I386EXT; |
| typedef struct { | typedef struct { |
| Line 201 extern I386CORE i386core; | Line 216 extern I386CORE i386core; |
| #define CPU_STATSAVE i386core.s | #define CPU_STATSAVE i386core.s |
| #define CPU_ADRSMASK i386core.s.cpu_stat.adrsmask | |
| #define CPU_RESETREQ i386core.s.cpu_stat.resetreq | |
| #define CPU_REMCLOCK i386core.s.remainclock | #define CPU_REMCLOCK i386core.s.remainclock |
| #define CPU_BASECLOCK i386core.s.baseclock | #define CPU_BASECLOCK i386core.s.baseclock |
| #define CPU_CLOCK i386core.s.clock | #define CPU_CLOCK i386core.s.clock |
| #define CPU_ADRSMASK i386core.s.adrsmask | |
| #define CPU_RESETREQ i386core.s.resetreq | |
| #define CPU_ITFBANK i386core.s.itfbank | #define CPU_ITFBANK i386core.s.itfbank |
| #define CPU_INPADRS i386core.s.inport | #define CPU_RAM_D000 i386core.s.ram_d0 |
| #define CPU_TYPE i386core.s.cpu_type | |
| #define CPUTYPE_V30 0x01 | |
| #define CPU_EXTMEM i386core.e.ext | #define CPU_EXTMEM i386core.e.ext |
| #define CPU_EXTMEMSIZE i386core.e.extsize | #define CPU_EXTMEMSIZE i386core.e.extsize |
| #define CPU_INPADRS i386core.e.inport | |
| extern BYTE iflags[]; | extern BYTE iflags[]; |
| extern jmp_buf exec_1step_jmpbuf; | extern sigjmp_buf exec_1step_jmpbuf; |
| /* | /* |
| Line 225 extern jmp_buf exec_1step_jmpbuf; | Line 245 extern jmp_buf exec_1step_jmpbuf; |
| #define CPU_VENDOR_3 0x6c65746e /* "ntel" */ | #define CPU_VENDOR_3 0x6c65746e /* "ntel" */ |
| /* version */ | /* version */ |
| #define CPU_FAMILY 6 | #define CPU_FAMILY 4 |
| #define CPU_MODEL 1 | #define CPU_MODEL 1 |
| #define CPU_STEPPING 3 | #define CPU_STEPPING 3 |
| Line 286 do { \ | Line 306 do { \ |
| #define CPU_STAT_SREG_INIT(n) \ | #define CPU_STAT_SREG_INIT(n) \ |
| do { \ | do { \ |
| descriptor_t sd; \ | descriptor_t sd; \ |
| memset(&CPU_STAT_SREG(n), 0, sizeof(CPU_STAT_SREG(n))); \ | \ |
| memset(&sd, 0, sizeof(sd)); \ | memset(&sd, 0, sizeof(sd)); \ |
| sd.u.seg.limit = 0xffff; \ | sd.u.seg.limit = 0xffff; \ |
| CPU_SET_SEGDESC_DEFAULT(&sd, (n), 0); \ | CPU_SET_SEGDESC_DEFAULT(&sd, (n), 0); \ |
| Line 343 do { \ | Line 363 do { \ |
| #define CPU_FLAGL CPU_STATSAVE.cpu_regs.eflags.b.l | #define CPU_FLAGL CPU_STATSAVE.cpu_regs.eflags.b.l |
| #define CPU_FLAGH CPU_STATSAVE.cpu_regs.eflags.b.h | #define CPU_FLAGH CPU_STATSAVE.cpu_regs.eflags.b.h |
| #define CPU_TRAP CPU_STATSAVE.cpu_stat.trap | #define CPU_TRAP CPU_STATSAVE.cpu_stat.trap |
| #define CPU_INPORT CPU_STATSAVE.cpu_stat.inport | // #define CPU_INPORT CPU_STATSAVE.cpu_stat.inport |
| #define CPU_OV CPU_STATSAVE.cpu_stat.ovflag | #define CPU_OV CPU_STATSAVE.cpu_stat.ovflag |
| #define C_FLAG (1 << 0) | #define C_FLAG (1 << 0) |
| Line 377 void set_flags(WORD new_flags, WORD mask | Line 397 void set_flags(WORD new_flags, WORD mask |
| void set_eflags(DWORD new_flags, DWORD mask); | void set_eflags(DWORD new_flags, DWORD mask); |
| #define CPU_TYPE CPU_STATSAVE.cpu_stat.cpu_type | |
| #define CPUTYPE_V30 0x01 | |
| #define CPU_INST_OP32 CPU_STATSAVE.cpu_inst.op_32 | #define CPU_INST_OP32 CPU_STATSAVE.cpu_inst.op_32 |
| #define CPU_INST_AS32 CPU_STATSAVE.cpu_inst.as_32 | #define CPU_INST_AS32 CPU_STATSAVE.cpu_inst.as_32 |
| #define CPU_INST_REPUSE CPU_STATSAVE.cpu_inst.rep_used | #define CPU_INST_REPUSE CPU_STATSAVE.cpu_inst.rep_used |
| Line 392 void set_eflags(DWORD new_flags, DWORD m | Line 409 void set_eflags(DWORD new_flags, DWORD m |
| #define CPU_STAT_CS_LIMIT CPU_STATSAVE.cpu_stat.sreg[CPU_CS_INDEX].u.seg.limit | #define CPU_STAT_CS_LIMIT CPU_STATSAVE.cpu_stat.sreg[CPU_CS_INDEX].u.seg.limit |
| #define CPU_STAT_CS_END CPU_STATSAVE.cpu_stat.sreg[CPU_CS_INDEX].u.seg.segend | #define CPU_STAT_CS_END CPU_STATSAVE.cpu_stat.sreg[CPU_CS_INDEX].u.seg.segend |
| #define CPU_STAT_ADRSMASK CPU_STATSAVE.cpu_stat.adrsmask | |
| #define CPU_STAT_SS32 CPU_STATSAVE.cpu_stat.ss_32 | #define CPU_STAT_SS32 CPU_STATSAVE.cpu_stat.ss_32 |
| #define CPU_STAT_RESETREQ CPU_STATSAVE.cpu_stat.resetreq | |
| #define CPU_STAT_PM CPU_STATSAVE.cpu_stat.protected_mode | #define CPU_STAT_PM CPU_STATSAVE.cpu_stat.protected_mode |
| #define CPU_STAT_VM86 CPU_STATSAVE.cpu_stat.vm86 | #define CPU_STAT_VM86 CPU_STATSAVE.cpu_stat.vm86 |
| #define CPU_STAT_PAGING CPU_STATSAVE.cpu_stat.paging | #define CPU_STAT_PAGING CPU_STATSAVE.cpu_stat.paging |
| Line 433 void set_eflags(DWORD new_flags, DWORD m | Line 452 void set_eflags(DWORD new_flags, DWORD m |
| /* | /* |
| * control register | * control register |
| */ | */ |
| #define CPU_MSW CPU_STATSAVE.cpu_sysregs.cr0 | |
| #define CPU_CR0 CPU_STATSAVE.cpu_sysregs.cr0 | #define CPU_CR0 CPU_STATSAVE.cpu_sysregs.cr0 |
| #define CPU_CR1 CPU_STATSAVE.cpu_sysregs.cr1 | #define CPU_CR1 CPU_STATSAVE.cpu_sysregs.cr1 |
| #define CPU_CR2 CPU_STATSAVE.cpu_sysregs.cr2 | #define CPU_CR2 CPU_STATSAVE.cpu_sysregs.cr2 |
| Line 455 void set_eflags(DWORD new_flags, DWORD m | Line 476 void set_eflags(DWORD new_flags, DWORD m |
| #define CPU_CR3_PD_MASK 0xfffff000 | #define CPU_CR3_PD_MASK 0xfffff000 |
| #define CPU_CR3_PWT (1 << 3) | #define CPU_CR3_PWT (1 << 3) |
| #define CPU_CR3_PCD (1 << 4) | #define CPU_CR3_PCD (1 << 4) |
| #define CPU_CR3_MASK (CPU_CR3_PD_MASK|CPU_CR3_PWT|CPU_CR3_PCD) | |
| #define CPU_CR4_VME (1 << 0) | #define CPU_CR4_VME (1 << 0) |
| #define CPU_CR4_PVI (1 << 1) | #define CPU_CR4_PVI (1 << 1) |
| Line 472 void set_eflags(DWORD new_flags, DWORD m | Line 494 void set_eflags(DWORD new_flags, DWORD m |
| void ia32_init(void); | void ia32_init(void); |
| void ia32reset(void); | void ia32reset(void); |
| void ia32shut(void); | |
| void ia32(void); | void ia32(void); |
| void ia32withtrap(void); | void ia32withtrap(void); |
| void ia32withdma(void); | void ia32withdma(void); |
| Line 506 extern WORD *reg16_b53[0x100]; | Line 529 extern WORD *reg16_b53[0x100]; |
| extern DWORD *reg32_b20[0x100]; | extern DWORD *reg32_b20[0x100]; |
| extern DWORD *reg32_b53[0x100]; | extern DWORD *reg32_b53[0x100]; |
| extern const char *reg8_str[8]; | |
| extern const char *reg16_str[8]; | |
| extern const char *reg32_str[8]; | |
| /* | /* |
| * Profile | * Misc. |
| */ | */ |
| #if defined(IA32_PROFILE_INSTRUCTION) | void gdtr_dump(DWORD base, DWORD limit); |
| extern UINT32 inst_1byte_count[2][256]; | void idtr_dump(DWORD base, DWORD limit); |
| extern UINT32 inst_2byte_count[2][256]; | void ldtr_dump(DWORD base, DWORD limit); |
| extern UINT32 ea16_count[24]; | void tr_dump(WORD selector, DWORD base, DWORD limit); |
| extern UINT32 ea32_count[24]; | |
| extern UINT32 sib0_count[256]; | |
| extern UINT32 sib1_count[256]; | |
| extern UINT32 sib2_count[256]; | |
| #define PROFILE_INC_INST_1BYTE(op) inst_1byte_count[CPU_INST_OP32][op]++ | |
| #define PROFILE_INC_INST_2BYTE(op) inst_2byte_count[CPU_INST_OP32][op]++ | |
| #define PROFILE_INC_EA16(idx) ea16_count[idx]++ | |
| #define PROFILE_INC_EA32(idx) ea32_count[idx]++ | |
| #define PROFILE_INC_SIB0(op) sib0_count[op]++ | |
| #define PROFILE_INC_SIB1(op) sib1_count[op]++ | |
| #define PROFILE_INC_SIB2(op) sib2_count[op]++ | |
| #else | |
| #define PROFILE_INC_INST_1BYTE(op) | |
| #define PROFILE_INC_INST_2BYTE(op) | |
| #define PROFILE_INC_EA16(idx) | |
| #define PROFILE_INC_EA32(idx) | |
| #define PROFILE_INC_SIB0(op) | |
| #define PROFILE_INC_SIB1(op) | |
| #define PROFILE_INC_SIB2(op) | |
| #endif | |
| #ifdef __cplusplus | #ifdef __cplusplus |
| } | } |