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Diff for /np2/i386c/ia32/cpu.h between versions 1.36 and 1.40

version 1.36, 2008/01/25 18:02:18 version 1.40, 2011/12/21 18:02:15
Line 1 Line 1
 /*      $Id$    */  
   
 /*  /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro   * Copyright (c) 2002-2003 NONAKA Kimihiro
  * All rights reserved.   * All rights reserved.
Line 174  typedef struct { Line 172  typedef struct {
         UINT8           hlt;          UINT8           hlt;
         UINT8           bp;     /* break point bitmap */          UINT8           bp;     /* break point bitmap */
         UINT8           bp_ev;  /* break point event */          UINT8           bp_ev;  /* break point event */
         UINT8           pad;  
           UINT8           backout_sp;     /* backout ESP, when exception */
   
         UINT32          pde_base;          UINT32          pde_base;
   
Line 360  extern sigjmp_buf exec_1step_jmpbuf; Line 359  extern sigjmp_buf exec_1step_jmpbuf;
 #define CPU_REGS_SREG(n)        CPU_STATSAVE.cpu_regs.sreg[(n)]  #define CPU_REGS_SREG(n)        CPU_STATSAVE.cpu_regs.sreg[(n)]
   
 #define CPU_STAT_SREG(n)        CPU_STATSAVE.cpu_stat.sreg[(n)]  #define CPU_STAT_SREG(n)        CPU_STATSAVE.cpu_stat.sreg[(n)]
 #define CPU_STAT_SREGBASE(n)    CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.segbase  #define CPU_STAT_SREGBASE(n)    CPU_STAT_SREG((n)).u.seg.segbase
 #define CPU_STAT_SREGEND(n)     CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.segend  #define CPU_STAT_SREGLIMIT(n)   CPU_STAT_SREG((n)).u.seg.limit
 #define CPU_STAT_SREGLIMIT(n)   CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.limit  
 #define CPU_STAT_SREG_CLEAR(n) \  
 do { \  
         memset(&CPU_STAT_SREG(n), 0, sizeof(descriptor_t)); \  
 } while (/*CONSTCOND*/ 0)  
 #define CPU_STAT_SREG_INIT(n) \  
 do { \  
         descriptor_t sd; \  
 \  
         memset(&sd, 0, sizeof(sd)); \  
         sd.u.seg.limit = 0xffff; \  
         CPU_SET_SEGDESC_DEFAULT(&sd, (n), 0); \  
         CPU_STAT_SREG(n) = sd; \  
 } while (/*CONSTCOND*/ 0)  
   
   
 #define CPU_AL          CPU_REGS_BYTEL(CPU_EAX_INDEX)  #define CPU_AL          CPU_REGS_BYTEL(CPU_EAX_INDEX)
Line 416  do { \ Line 401  do { \
 #define CPU_FS          CPU_REGS_SREG(CPU_FS_INDEX)  #define CPU_FS          CPU_REGS_SREG(CPU_FS_INDEX)
 #define CPU_GS          CPU_REGS_SREG(CPU_GS_INDEX)  #define CPU_GS          CPU_REGS_SREG(CPU_GS_INDEX)
   
   #define CPU_ES_DESC     CPU_STAT_SREG(CPU_ES_INDEX)
   #define CPU_CS_DESC     CPU_STAT_SREG(CPU_CS_INDEX)
   #define CPU_SS_DESC     CPU_STAT_SREG(CPU_SS_INDEX)
   #define CPU_DS_DESC     CPU_STAT_SREG(CPU_DS_INDEX)
   #define CPU_FS_DESC     CPU_STAT_SREG(CPU_FS_INDEX)
   #define CPU_GS_DESC     CPU_STAT_SREG(CPU_GS_INDEX)
   
 #define ES_BASE         CPU_STAT_SREGBASE(CPU_ES_INDEX)  #define ES_BASE         CPU_STAT_SREGBASE(CPU_ES_INDEX)
 #define CS_BASE         CPU_STAT_SREGBASE(CPU_CS_INDEX)  #define CS_BASE         CPU_STAT_SREGBASE(CPU_CS_INDEX)
 #define SS_BASE         CPU_STAT_SREGBASE(CPU_SS_INDEX)  #define SS_BASE         CPU_STAT_SREGBASE(CPU_SS_INDEX)
Line 458  do { \ Line 450  do { \
 #define REAL_FLAGREG    ((CPU_FLAG & 0xf7ff) | (CPU_OV ? O_FLAG : 0) | 2)  #define REAL_FLAGREG    ((CPU_FLAG & 0xf7ff) | (CPU_OV ? O_FLAG : 0) | 2)
 #define REAL_EFLAGREG   ((CPU_EFLAG & 0xfffff7ff) | (CPU_OV ? O_FLAG : 0) | 2)  #define REAL_EFLAGREG   ((CPU_EFLAG & 0xfffff7ff) | (CPU_OV ? O_FLAG : 0) | 2)
   
 void set_flags(UINT16 new_flags, UINT16 mask);  void CPUCALL set_flags(UINT16 new_flags, UINT16 mask);
 void set_eflags(UINT32 new_flags, UINT32 mask);  void CPUCALL set_eflags(UINT32 new_flags, UINT32 mask);
   
   
 #define CPU_INST_OP32           CPU_STATSAVE.cpu_inst.op_32  #define CPU_INST_OP32           CPU_STATSAVE.cpu_inst.op_32
Line 472  void set_eflags(UINT32 new_flags, UINT32 Line 464  void set_eflags(UINT32 new_flags, UINT32
   
 #define CPU_STAT_CS_BASE        CPU_STAT_SREGBASE(CPU_CS_INDEX)  #define CPU_STAT_CS_BASE        CPU_STAT_SREGBASE(CPU_CS_INDEX)
 #define CPU_STAT_CS_LIMIT       CPU_STAT_SREGLIMIT(CPU_CS_INDEX)  #define CPU_STAT_CS_LIMIT       CPU_STAT_SREGLIMIT(CPU_CS_INDEX)
 #define CPU_STAT_CS_END         CPU_STAT_SREGEND(CPU_CS_INDEX)  
   
 #define CPU_STAT_ADRSMASK       CPU_STATSAVE.cpu_stat.adrsmask  #define CPU_STAT_ADRSMASK       CPU_STATSAVE.cpu_stat.adrsmask
 #define CPU_STAT_SS32           CPU_STATSAVE.cpu_stat.ss_32  #define CPU_STAT_SS32           CPU_STATSAVE.cpu_stat.ss_32
Line 481  void set_eflags(UINT32 new_flags, UINT32 Line 472  void set_eflags(UINT32 new_flags, UINT32
 #define CPU_STAT_PAGING         CPU_STATSAVE.cpu_stat.paging  #define CPU_STAT_PAGING         CPU_STATSAVE.cpu_stat.paging
 #define CPU_STAT_VM86           CPU_STATSAVE.cpu_stat.vm86  #define CPU_STAT_VM86           CPU_STATSAVE.cpu_stat.vm86
 #define CPU_STAT_WP             CPU_STATSAVE.cpu_stat.page_wp  #define CPU_STAT_WP             CPU_STATSAVE.cpu_stat.page_wp
 #define CPU_STAT_CPL            CPU_STAT_SREG(CPU_CS_INDEX).rpl  #define CPU_STAT_CPL            CPU_CS_DESC.rpl
 #define CPU_STAT_USER_MODE      CPU_STATSAVE.cpu_stat.user_mode  #define CPU_STAT_USER_MODE      CPU_STATSAVE.cpu_stat.user_mode
 #define CPU_STAT_PDE_BASE       CPU_STATSAVE.cpu_stat.pde_base  #define CPU_STAT_PDE_BASE       CPU_STATSAVE.cpu_stat.pde_base
   #define CPU_SET_PREV_ESP1(esp) \
   do { \
           CPU_STATSAVE.cpu_stat.backout_sp = 1; \
           CPU_PREV_ESP = (esp); \
   } while (/*CONSTCOND*/0)
   #define CPU_SET_PREV_ESP()      CPU_SET_PREV_ESP1(CPU_ESP)
   #define CPU_CLEAR_PREV_ESP() \
   do { \
           CPU_STATSAVE.cpu_stat.backout_sp = 0; \
   } while (/*CONSTCOND*/0)
   
 #define CPU_STAT_HLT            CPU_STATSAVE.cpu_stat.hlt  #define CPU_STAT_HLT            CPU_STATSAVE.cpu_stat.hlt
   
Line 503  void set_eflags(UINT32 new_flags, UINT32 Line 504  void set_eflags(UINT32 new_flags, UINT32
   
 #define CPU_MODE_SUPERVISER     0  #define CPU_MODE_SUPERVISER     0
 #define CPU_MODE_USER           (1 << 3)  #define CPU_MODE_USER           (1 << 3)
 #define CPU_SET_CPL(cpl) \  
 do { \  
         UINT8 __t = (UINT8)((cpl) & 3); \  
         CPU_STAT_CPL = __t; \  
         CPU_STAT_USER_MODE = (__t == 3) ? CPU_MODE_USER : CPU_MODE_SUPERVISER; \  
 } while (/*CONSTCOND*/ 0)  
   
 #define CPU_CLI \  #define CPU_CLI \
 do { \  do { \
Line 528  do { \ Line 523  do { \
 #define CPU_IDTR_BASE   CPU_STATSAVE.cpu_sysregs.idtr_base  #define CPU_IDTR_BASE   CPU_STATSAVE.cpu_sysregs.idtr_base
 #define CPU_LDTR        CPU_STATSAVE.cpu_sysregs.ldtr  #define CPU_LDTR        CPU_STATSAVE.cpu_sysregs.ldtr
 #define CPU_LDTR_DESC   CPU_STATSAVE.cpu_stat.ldtr  #define CPU_LDTR_DESC   CPU_STATSAVE.cpu_stat.ldtr
 #define CPU_LDTR_BASE   CPU_STATSAVE.cpu_stat.ldtr.u.seg.segbase  #define CPU_LDTR_BASE   CPU_LDTR_DESC.u.seg.segbase
 #define CPU_LDTR_END    CPU_STATSAVE.cpu_stat.ldtr.u.seg.segend  #define CPU_LDTR_LIMIT  CPU_LDTR_DESC.u.seg.limit
 #define CPU_LDTR_LIMIT  CPU_STATSAVE.cpu_stat.ldtr.u.seg.limit  
 #define CPU_TR          CPU_STATSAVE.cpu_sysregs.tr  #define CPU_TR          CPU_STATSAVE.cpu_sysregs.tr
 #define CPU_TR_DESC     CPU_STATSAVE.cpu_stat.tr  #define CPU_TR_DESC     CPU_STATSAVE.cpu_stat.tr
 #define CPU_TR_BASE     CPU_STATSAVE.cpu_stat.tr.u.seg.segbase  #define CPU_TR_BASE     CPU_TR_DESC.u.seg.segbase
 #define CPU_TR_END      CPU_STATSAVE.cpu_stat.tr.u.seg.segend  #define CPU_TR_LIMIT    CPU_TR_DESC.u.seg.limit
 #define CPU_TR_LIMIT    CPU_STATSAVE.cpu_stat.tr.u.seg.limit  
   
 /*  /*
  * control register   * control register
Line 626  void ia32a20enable(BOOL enable); Line 619  void ia32a20enable(BOOL enable);
 void ia32(void);  void ia32(void);
 void ia32_step(void);  void ia32_step(void);
 void CPUCALL ia32_interrupt(int vect, int soft);  void CPUCALL ia32_interrupt(int vect, int soft);
 void CPUCALL ia32_exception(int vect, int p1, int p2);  
   
 void exec_1step(void);  void exec_1step(void);
 #define INST_PREFIX     (1 << 0)  #define INST_PREFIX     (1 << 0)
Line 639  void ia32_panic(const char *buf, ...); Line 631  void ia32_panic(const char *buf, ...);
   
 void ia32_bioscall(void);  void ia32_bioscall(void);
   
 void FASTCALL change_pm(BOOL onoff);  void CPUCALL change_pm(BOOL onoff);
 void FASTCALL change_vm(BOOL onoff);  void CPUCALL change_vm(BOOL onoff);
 void FASTCALL change_pg(BOOL onoff);  void CPUCALL change_pg(BOOL onoff);
   
   void CPUCALL set_cr3(UINT32 new_cr3);
   void CPUCALL set_cpl(int new_cpl);
   
 extern const UINT8 iflags[];  extern const UINT8 iflags[];
 #define szpcflag        iflags  #define szpcflag        iflags
Line 740  void idtr_dump(UINT32 base, UINT limit); Line 735  void idtr_dump(UINT32 base, UINT limit);
 void ldtr_dump(UINT32 base, UINT limit);  void ldtr_dump(UINT32 base, UINT limit);
 void tr_dump(UINT16 selector, UINT32 base, UINT limit);  void tr_dump(UINT16 selector, UINT32 base, UINT limit);
 UINT32 pde_dump(UINT32 base, int idx);  UINT32 pde_dump(UINT32 base, int idx);
   void segdesc_dump(descriptor_t *sdp);
 UINT32 convert_laddr_to_paddr(UINT32 laddr);  UINT32 convert_laddr_to_paddr(UINT32 laddr);
 UINT32 convert_vaddr_to_paddr(unsigned int idx, UINT32 offset);  UINT32 convert_vaddr_to_paddr(unsigned int idx, UINT32 offset);
   
Removed from v.1.36  
changed lines
  Added in v.1.40

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