| version 1.34, 2005/03/16 06:05:18 | version 1.41, 2011/12/21 18:07:57 | 
| Line 1 | Line 1 | 
 | /*      $Id$    */ |  | 
 |  |  | 
 | /* | /* | 
 | * Copyright (c) 2002-2003 NONAKA Kimihiro | * Copyright (c) 2002-2003 NONAKA Kimihiro | 
 | * All rights reserved. | * All rights reserved. | 
| Line 174  typedef struct { | Line 172  typedef struct { | 
 | UINT8           hlt; | UINT8           hlt; | 
 | UINT8           bp;     /* break point bitmap */ | UINT8           bp;     /* break point bitmap */ | 
 | UINT8           bp_ev;  /* break point event */ | UINT8           bp_ev;  /* break point event */ | 
| UINT8           pad; |  | 
|  | UINT8           backout_sp;     /* backout ESP, when exception */ | 
 |  |  | 
 | UINT32          pde_base; | UINT32          pde_base; | 
 |  |  | 
| Line 214  typedef struct { | Line 213  typedef struct { | 
 | } FPU_REGS; | } FPU_REGS; | 
 |  |  | 
 | typedef struct { | typedef struct { | 
| UINT8           valid;  /* ¥ì¥¸¥¹¥¿Í¸ú */ | UINT8           valid;  /* ¥ì¥¸¥¹¥¿Í¸ú */ | 
| UINT8           sign;   /* É乿 */ | UINT8           sign;   /* É乿 */ | 
| UINT8           zero;   /* ¥¼¥í */ | UINT8           zero;   /* ¥¼¥í */ | 
| UINT8           inf;    /* ¡ç */ | UINT8           inf;    /* ¡ç */ | 
 | UINT8           nan;    /* NaN */ | UINT8           nan;    /* NaN */ | 
| UINT8           denorm; /* ÈóÀµµ¬²½ */ | UINT8           denorm; /* ñýÜè¥å¡×ð¨¾ç·ö */ | 
| SINT16          exp;    /* »Ø¿ôÉô */ | SINT16          exp;    /* ëì®èʲñ㥣 */ | 
| UINT64          num;    /* ¾®¿ôÉô */ | UINT64          num;    /* ê²¾èʲñ㥣 */ | 
 | } FP_REG; | } FP_REG; | 
 |  |  | 
 | typedef struct { | typedef struct { | 
| UINT8           top;    /* ¡¦¥±¡¦¥½¡¦¥Æ¡¦¥Ã¡¼¥Õ¥Æ¥è */ | UINT8           top;    /* ¥¹¥¿¥Ã¥¯°ÌÃÖ */ | 
| UINT8           pc;     /* ¥¿¥³¥Ê¥ë */ | UINT8           pc;     /* ÀºÅÙ */ | 
| UINT8           rc;     /* ¥¨¥ó¡¢*/ | UINT8           rc;     /* ´Ý¤á */ | 
 | UINT8           dmy[1]; | UINT8           dmy[1]; | 
 |  |  | 
 | FP_REG          reg[FPU_REG_NUM]; | FP_REG          reg[FPU_REG_NUM]; | 
| Line 265  typedef struct { | Line 264  typedef struct { | 
 | } I386EXT; | } I386EXT; | 
 |  |  | 
 | typedef struct { | typedef struct { | 
| I386STAT        s;                              /* STATsave¡¢¥ª¡¢ø¦öÇ¥í */ | I386STAT        s;                              /* STATsaveåáÊå£ìåâ¶ç¡¦¥¨ */ | 
 | I386EXT         e; | I386EXT         e; | 
 | } I386CORE; | } I386CORE; | 
 |  |  | 
| Line 360  extern sigjmp_buf exec_1step_jmpbuf; | Line 359  extern sigjmp_buf exec_1step_jmpbuf; | 
 | #define CPU_REGS_SREG(n)        CPU_STATSAVE.cpu_regs.sreg[(n)] | #define CPU_REGS_SREG(n)        CPU_STATSAVE.cpu_regs.sreg[(n)] | 
 |  |  | 
 | #define CPU_STAT_SREG(n)        CPU_STATSAVE.cpu_stat.sreg[(n)] | #define CPU_STAT_SREG(n)        CPU_STATSAVE.cpu_stat.sreg[(n)] | 
| #define CPU_STAT_SREGBASE(n)    CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.segbase | #define CPU_STAT_SREGBASE(n)    CPU_STAT_SREG((n)).u.seg.segbase | 
| #define CPU_STAT_SREGEND(n)     CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.segend | #define CPU_STAT_SREGLIMIT(n)   CPU_STAT_SREG((n)).u.seg.limit | 
| #define CPU_STAT_SREGLIMIT(n)   CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.limit |  | 
| #define CPU_STAT_SREG_CLEAR(n) \ |  | 
| do { \ |  | 
| memset(&CPU_STAT_SREG(n), 0, sizeof(descriptor_t)); \ |  | 
| } while (/*CONSTCOND*/ 0) |  | 
| #define CPU_STAT_SREG_INIT(n) \ |  | 
| do { \ |  | 
| descriptor_t sd; \ |  | 
| \ |  | 
| memset(&sd, 0, sizeof(sd)); \ |  | 
| sd.u.seg.limit = 0xffff; \ |  | 
| CPU_SET_SEGDESC_DEFAULT(&sd, (n), 0); \ |  | 
| CPU_STAT_SREG(n) = sd; \ |  | 
| } while (/*CONSTCOND*/ 0) |  | 
 |  |  | 
 |  |  | 
 | #define CPU_AL          CPU_REGS_BYTEL(CPU_EAX_INDEX) | #define CPU_AL          CPU_REGS_BYTEL(CPU_EAX_INDEX) | 
| Line 416  do { \ | Line 401  do { \ | 
 | #define CPU_FS          CPU_REGS_SREG(CPU_FS_INDEX) | #define CPU_FS          CPU_REGS_SREG(CPU_FS_INDEX) | 
 | #define CPU_GS          CPU_REGS_SREG(CPU_GS_INDEX) | #define CPU_GS          CPU_REGS_SREG(CPU_GS_INDEX) | 
 |  |  | 
 |  | #define CPU_ES_DESC     CPU_STAT_SREG(CPU_ES_INDEX) | 
 |  | #define CPU_CS_DESC     CPU_STAT_SREG(CPU_CS_INDEX) | 
 |  | #define CPU_SS_DESC     CPU_STAT_SREG(CPU_SS_INDEX) | 
 |  | #define CPU_DS_DESC     CPU_STAT_SREG(CPU_DS_INDEX) | 
 |  | #define CPU_FS_DESC     CPU_STAT_SREG(CPU_FS_INDEX) | 
 |  | #define CPU_GS_DESC     CPU_STAT_SREG(CPU_GS_INDEX) | 
 |  |  | 
 | #define ES_BASE         CPU_STAT_SREGBASE(CPU_ES_INDEX) | #define ES_BASE         CPU_STAT_SREGBASE(CPU_ES_INDEX) | 
 | #define CS_BASE         CPU_STAT_SREGBASE(CPU_CS_INDEX) | #define CS_BASE         CPU_STAT_SREGBASE(CPU_CS_INDEX) | 
 | #define SS_BASE         CPU_STAT_SREGBASE(CPU_SS_INDEX) | #define SS_BASE         CPU_STAT_SREGBASE(CPU_SS_INDEX) | 
| Line 458  do { \ | Line 450  do { \ | 
 | #define REAL_FLAGREG    ((CPU_FLAG & 0xf7ff) | (CPU_OV ? O_FLAG : 0) | 2) | #define REAL_FLAGREG    ((CPU_FLAG & 0xf7ff) | (CPU_OV ? O_FLAG : 0) | 2) | 
 | #define REAL_EFLAGREG   ((CPU_EFLAG & 0xfffff7ff) | (CPU_OV ? O_FLAG : 0) | 2) | #define REAL_EFLAGREG   ((CPU_EFLAG & 0xfffff7ff) | (CPU_OV ? O_FLAG : 0) | 2) | 
 |  |  | 
| #if !defined(IA32_DONT_USE_SET_EFLAGS_FUNCTION) | void CPUCALL set_flags(UINT16 new_flags, UINT16 mask); | 
| void set_flags(UINT16 new_flags, UINT16 mask); | void CPUCALL set_eflags(UINT32 new_flags, UINT32 mask); | 
| void set_eflags(UINT32 new_flags, UINT32 mask); |  | 
| #endif |  | 
 |  |  | 
 |  |  | 
 | #define CPU_INST_OP32           CPU_STATSAVE.cpu_inst.op_32 | #define CPU_INST_OP32           CPU_STATSAVE.cpu_inst.op_32 | 
| Line 474  void set_eflags(UINT32 new_flags, UINT32 | Line 464  void set_eflags(UINT32 new_flags, UINT32 | 
 |  |  | 
 | #define CPU_STAT_CS_BASE        CPU_STAT_SREGBASE(CPU_CS_INDEX) | #define CPU_STAT_CS_BASE        CPU_STAT_SREGBASE(CPU_CS_INDEX) | 
 | #define CPU_STAT_CS_LIMIT       CPU_STAT_SREGLIMIT(CPU_CS_INDEX) | #define CPU_STAT_CS_LIMIT       CPU_STAT_SREGLIMIT(CPU_CS_INDEX) | 
 | #define CPU_STAT_CS_END         CPU_STAT_SREGEND(CPU_CS_INDEX) |  | 
 |  |  | 
 | #define CPU_STAT_ADRSMASK       CPU_STATSAVE.cpu_stat.adrsmask | #define CPU_STAT_ADRSMASK       CPU_STATSAVE.cpu_stat.adrsmask | 
 | #define CPU_STAT_SS32           CPU_STATSAVE.cpu_stat.ss_32 | #define CPU_STAT_SS32           CPU_STATSAVE.cpu_stat.ss_32 | 
| Line 483  void set_eflags(UINT32 new_flags, UINT32 | Line 472  void set_eflags(UINT32 new_flags, UINT32 | 
 | #define CPU_STAT_PAGING         CPU_STATSAVE.cpu_stat.paging | #define CPU_STAT_PAGING         CPU_STATSAVE.cpu_stat.paging | 
 | #define CPU_STAT_VM86           CPU_STATSAVE.cpu_stat.vm86 | #define CPU_STAT_VM86           CPU_STATSAVE.cpu_stat.vm86 | 
 | #define CPU_STAT_WP             CPU_STATSAVE.cpu_stat.page_wp | #define CPU_STAT_WP             CPU_STATSAVE.cpu_stat.page_wp | 
| #define CPU_STAT_CPL            CPU_STAT_SREG(CPU_CS_INDEX).rpl | #define CPU_STAT_CPL            CPU_CS_DESC.rpl | 
 | #define CPU_STAT_USER_MODE      CPU_STATSAVE.cpu_stat.user_mode | #define CPU_STAT_USER_MODE      CPU_STATSAVE.cpu_stat.user_mode | 
 | #define CPU_STAT_PDE_BASE       CPU_STATSAVE.cpu_stat.pde_base | #define CPU_STAT_PDE_BASE       CPU_STATSAVE.cpu_stat.pde_base | 
 |  | #define CPU_SET_PREV_ESP1(esp) \ | 
 |  | do { \ | 
 |  | CPU_STATSAVE.cpu_stat.backout_sp = 1; \ | 
 |  | CPU_PREV_ESP = (esp); \ | 
 |  | } while (/*CONSTCOND*/0) | 
 |  | #define CPU_SET_PREV_ESP()      CPU_SET_PREV_ESP1(CPU_ESP) | 
 |  | #define CPU_CLEAR_PREV_ESP() \ | 
 |  | do { \ | 
 |  | CPU_STATSAVE.cpu_stat.backout_sp = 0; \ | 
 |  | } while (/*CONSTCOND*/0) | 
 |  |  | 
 | #define CPU_STAT_HLT            CPU_STATSAVE.cpu_stat.hlt | #define CPU_STAT_HLT            CPU_STATSAVE.cpu_stat.hlt | 
 |  |  | 
| Line 503  void set_eflags(UINT32 new_flags, UINT32 | Line 502  void set_eflags(UINT32 new_flags, UINT32 | 
 | #define CPU_STAT_EXCEPTION_COUNTER_INC()        CPU_STATSAVE.cpu_stat.nerror++ | #define CPU_STAT_EXCEPTION_COUNTER_INC()        CPU_STATSAVE.cpu_stat.nerror++ | 
 | #define CPU_STAT_EXCEPTION_COUNTER_CLEAR()      CPU_STATSAVE.cpu_stat.nerror = 0 | #define CPU_STAT_EXCEPTION_COUNTER_CLEAR()      CPU_STATSAVE.cpu_stat.nerror = 0 | 
 |  |  | 
 | #define CPU_PREFETCH_CLEAR() |  | 
 | #define CPU_PREFETCHQ_REMAIN_ADD(d) |  | 
 | #define CPU_PREFETCHQ_REMAIN_SUB(d) |  | 
 |  |  | 
 | #define CPU_MODE_SUPERVISER     0 | #define CPU_MODE_SUPERVISER     0 | 
 | #define CPU_MODE_USER           (1 << 3) | #define CPU_MODE_USER           (1 << 3) | 
 | #define CPU_SET_CPL(cpl) \ |  | 
 | do { \ |  | 
 | UINT8 __t = (UINT8)((cpl) & 3); \ |  | 
 | CPU_STAT_CPL = __t; \ |  | 
 | CPU_STAT_USER_MODE = (__t == 3) ? CPU_MODE_USER : CPU_MODE_SUPERVISER; \ |  | 
 | } while (/*CONSTCOND*/ 0) |  | 
 |  |  | 
 | #define CPU_CLI \ | #define CPU_CLI \ | 
 | do { \ | do { \ | 
| Line 534  do { \ | Line 523  do { \ | 
 | #define CPU_IDTR_BASE   CPU_STATSAVE.cpu_sysregs.idtr_base | #define CPU_IDTR_BASE   CPU_STATSAVE.cpu_sysregs.idtr_base | 
 | #define CPU_LDTR        CPU_STATSAVE.cpu_sysregs.ldtr | #define CPU_LDTR        CPU_STATSAVE.cpu_sysregs.ldtr | 
 | #define CPU_LDTR_DESC   CPU_STATSAVE.cpu_stat.ldtr | #define CPU_LDTR_DESC   CPU_STATSAVE.cpu_stat.ldtr | 
| #define CPU_LDTR_BASE   CPU_STATSAVE.cpu_stat.ldtr.u.seg.segbase | #define CPU_LDTR_BASE   CPU_LDTR_DESC.u.seg.segbase | 
| #define CPU_LDTR_END    CPU_STATSAVE.cpu_stat.ldtr.u.seg.segend | #define CPU_LDTR_LIMIT  CPU_LDTR_DESC.u.seg.limit | 
| #define CPU_LDTR_LIMIT  CPU_STATSAVE.cpu_stat.ldtr.u.seg.limit |  | 
 | #define CPU_TR          CPU_STATSAVE.cpu_sysregs.tr | #define CPU_TR          CPU_STATSAVE.cpu_sysregs.tr | 
 | #define CPU_TR_DESC     CPU_STATSAVE.cpu_stat.tr | #define CPU_TR_DESC     CPU_STATSAVE.cpu_stat.tr | 
| #define CPU_TR_BASE     CPU_STATSAVE.cpu_stat.tr.u.seg.segbase | #define CPU_TR_BASE     CPU_TR_DESC.u.seg.segbase | 
| #define CPU_TR_END      CPU_STATSAVE.cpu_stat.tr.u.seg.segend | #define CPU_TR_LIMIT    CPU_TR_DESC.u.seg.limit | 
| #define CPU_TR_LIMIT    CPU_STATSAVE.cpu_stat.tr.u.seg.limit |  | 
 |  |  | 
 | /* | /* | 
 | * control register | * control register | 
| Line 632  void ia32a20enable(BOOL enable); | Line 619  void ia32a20enable(BOOL enable); | 
 | void ia32(void); | void ia32(void); | 
 | void ia32_step(void); | void ia32_step(void); | 
 | void CPUCALL ia32_interrupt(int vect, int soft); | void CPUCALL ia32_interrupt(int vect, int soft); | 
 | void CPUCALL ia32_exception(int vect, int p1, int p2); |  | 
 |  |  | 
 | void exec_1step(void); | void exec_1step(void); | 
 | #define INST_PREFIX     (1 << 0) | #define INST_PREFIX     (1 << 0) | 
| Line 645  void ia32_panic(const char *buf, ...); | Line 631  void ia32_panic(const char *buf, ...); | 
 |  |  | 
 | void ia32_bioscall(void); | void ia32_bioscall(void); | 
 |  |  | 
| void FASTCALL change_pm(BOOL onoff); | void CPUCALL change_pm(BOOL onoff); | 
| void FASTCALL change_vm(BOOL onoff); | void CPUCALL change_vm(BOOL onoff); | 
| void FASTCALL change_pg(BOOL onoff); | void CPUCALL change_pg(BOOL onoff); | 
|  |  | 
|  | void CPUCALL set_cr3(UINT32 new_cr3); | 
|  | void CPUCALL set_cpl(int new_cpl); | 
 |  |  | 
 | extern const UINT8 iflags[]; | extern const UINT8 iflags[]; | 
 | #define szpcflag        iflags | #define szpcflag        iflags | 
| Line 695  void dbg_printf(const char *str, ...); | Line 684  void dbg_printf(const char *str, ...); | 
 | #define FPU_REG(i)              FPU_STAT.reg[i] | #define FPU_REG(i)              FPU_STAT.reg[i] | 
 |  |  | 
 | /* FPU status register */ | /* FPU status register */ | 
| #define FP_IE_FLAG      (1 << 0)        /* ¥Õ¥ª¥¯ùè¥Ï¥Ë¡¼¥³*/ | #define FP_IE_FLAG      (1 << 0)        /* ̵¸ú¤Êưºî */ | 
| #define FP_DE_FLAG      (1 << 1)        /* ¥Ç¥Î¡¼¥Þ¥é¥¤¥º¥É¡¦¥ª¥Ú¥é¥ó¥É */ | #define FP_DE_FLAG      (1 << 1)        /* ¥Ç¥Î¡¼¥Þ¥é¥¤¥º¥É¡¦¥ª¥Ú¥é¥ó¥É */ | 
| #define FP_ZE_FLAG      (1 << 2)        /* ¥¼¥í¤Ë¤è¤ë½ü»» */ | #define FP_ZE_FLAG      (1 << 2)        /* ¥¼¥í¤Ë¤è¤ë½ü»» */ | 
| #define FP_OE_FLAG      (1 << 3)        /* ¥ª¡¼¥Ð¡¼¥Õ¥í¡¼ */ | #define FP_OE_FLAG      (1 << 3)        /* ¥ª¡¼¥Ð¡¼¥Õ¥í¡¼ */ | 
| #define FP_UE_FLAG      (1 << 4)        /* ¥¢¥ó¥À¡¼¥Õ¥í¡¼ */ | #define FP_UE_FLAG      (1 << 4)        /* ¥¢¥ó¥À¡¼¥Õ¥í¡¼ */ | 
| #define FP_PE_FLAG      (1 << 5)        /* ÀºÅÙ */ | #define FP_PE_FLAG      (1 << 5)        /* ÀºÅÙ */ | 
| #define FP_SF_FLAG      (1 << 6)        /* ¥¹¥¿¥Ã¥¯¥Õ¥©¥ë¥È */ | #define FP_SF_FLAG      (1 << 6)        /* ¥¹¥¿¥Ã¥¯¥Õ¥©¥ë¥È */ | 
| #define FP_ES_FLAG      (1 << 7)        /* ¥¨¥é¡¼¥µ¥Þ¥ê¥¹¥Æ¡¼¥¿¥¹ */ | #define FP_ES_FLAG      (1 << 7)        /* ¥¨¥é¡¼¥µ¥Þ¥ê¥¹¥Æ¡¼¥¿¥¹ */ | 
| #define FP_C0_FLAG      (1 << 8)        /* ¾ò·ï¥³¡¼¥É */ | #define FP_C0_FLAG      (1 << 8)        /* ¾ò·ï¥³¡¼¥É */ | 
| #define FP_C1_FLAG      (1 << 9)        /* ¾ò·ï¥³¡¼¥É */ | #define FP_C1_FLAG      (1 << 9)        /* ¾ò·ï¥³¡¼¥É */ | 
| #define FP_C2_FLAG      (1 << 10)       /* ¾ò·ï¥³¡¼¥É */ | #define FP_C2_FLAG      (1 << 10)       /* ¾ò·ï¥³¡¼¥É */ | 
| #define FP_TOP_FLAG     (7 << 11)       /* ¥¹¥¿¥Ã¥¯¥Ý¥¤¥ó¥È¤Î¥È¥Ã¥× */ | #define FP_TOP_FLAG     (7 << 11)       /* ¥¹¥¿¥Ã¥¯¥Ý¥¤¥ó¥È¤Î¥È¥Ã¥× */ | 
| #define FP_C3_FLAG      (1 << 14)       /* ¾ò·ï¥³¡¼¥É */ | #define FP_C3_FLAG      (1 << 14)       /* ¾ò·ï¥³¡¼¥É */ | 
| #define FP_B_FLAG       (1 << 15)       /* FPU ¥Ó¥¸¡¼ */ | #define FP_B_FLAG       (1 << 15)       /* FPU ¥Ó¥¸¡¼ */ | 
 |  |  | 
 | #define FP_TOP_SHIFT    11 | #define FP_TOP_SHIFT    11 | 
 | #define FP_TOP_GET()    ((FPU_STATUSWORD & FP_TOP_FLAG) >> FP_TOP_SHIFT) | #define FP_TOP_GET()    ((FPU_STATUSWORD & FP_TOP_FLAG) >> FP_TOP_SHIFT) | 
| Line 724  do { \ | Line 713  do { \ | 
 | } while (/*CONSTCOND*/0) | } while (/*CONSTCOND*/0) | 
 |  |  | 
 | /* FPU control register */ | /* FPU control register */ | 
| #define FP_CTRL_PC_SHIFT        8       /* ÅÙÀ©¸æ */ | #define FP_CTRL_PC_SHIFT        8       /* 精度é襫êÀ¡£ */ | 
| #define FP_CTRL_RC_SHIFT        10      /* ´Ý¤áÀ©¸æ */ | #define FP_CTRL_RC_SHIFT        10      /* 躥¯åâ¢ç°¸êÀ¡£ */ | 
 |  |  | 
| #define FP_CTRL_PC_24           0       /* ¥Æ¥¢¥¿¥³¥Ê¥ë */ | #define FP_CTRL_PC_24           0       /* éíÐ饤¥»ê¼¥ò */ | 
| #define FP_CTRL_PC_53           1       /* ¥Ì¥ï¥¿¥³¥Ê¥ë */ | #define FP_CTRL_PC_53           1       /* éàºé¥¤¥»ê¼¥ò */ | 
| #define FP_CTRL_PC_64           3       /* ¥¦¥Í¥È¡¦¥¿¥³¥Ê¥ë */ | #define FP_CTRL_PC_64           3       /* ë롣꾥ªî´¥»ê¼¥ò */ | 
 |  |  | 
 | #define FP_CTRL_RC_NEAREST_EVEN 0 | #define FP_CTRL_RC_NEAREST_EVEN 0 | 
 | #define FP_CTRL_RC_DOWN         1 | #define FP_CTRL_RC_DOWN         1 | 
| Line 746  void idtr_dump(UINT32 base, UINT limit); | Line 735  void idtr_dump(UINT32 base, UINT limit); | 
 | void ldtr_dump(UINT32 base, UINT limit); | void ldtr_dump(UINT32 base, UINT limit); | 
 | void tr_dump(UINT16 selector, UINT32 base, UINT limit); | void tr_dump(UINT16 selector, UINT32 base, UINT limit); | 
 | UINT32 pde_dump(UINT32 base, int idx); | UINT32 pde_dump(UINT32 base, int idx); | 
 |  | void segdesc_dump(descriptor_t *sdp); | 
 | UINT32 convert_laddr_to_paddr(UINT32 laddr); | UINT32 convert_laddr_to_paddr(UINT32 laddr); | 
 | UINT32 convert_vaddr_to_paddr(unsigned int idx, UINT32 offset); | UINT32 convert_vaddr_to_paddr(unsigned int idx, UINT32 offset); | 
 |  |  |