--- np2/i386c/ia32/cpu.h	2004/02/03 14:49:39	1.12
+++ np2/i386c/ia32/cpu.h	2004/02/05 16:43:44	1.14
@@ -1,4 +1,4 @@
-/*	$Id: cpu.h,v 1.12 2004/02/03 14:49:39 monaka Exp $	*/
+/*	$Id: cpu.h,v 1.14 2004/02/05 16:43:44 monaka Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -121,9 +121,10 @@ typedef struct {
 	WORD		sreg[CPU_SEGREG_NUM];
 
 	REG32		eflags;
-
 	REG32		eip;
+
 	REG32		prev_eip;
+	REG32		prev_esp;
 
 	DWORD		tr[CPU_TEST_REG_NUM];
 	DWORD		dr[CPU_DEBUG_REG_NUM];
@@ -137,8 +138,6 @@ typedef struct {
 
 	WORD		ldtr;
 	WORD		tr;
-	descriptor_t	ldtr_desc;
-	descriptor_t	tr_desc;
 
 	DWORD		cr0;
 	DWORD		cr1;
@@ -150,6 +149,8 @@ typedef struct {
 
 typedef struct {
 	descriptor_t	sreg[CPU_SEGREG_NUM];
+	descriptor_t	ldtr_desc;
+	descriptor_t	tr_desc;
 
 	UINT32		adrsmask;
 	DWORD		ovflag;
@@ -157,9 +158,10 @@ typedef struct {
 	BYTE		ss_32;
 	BYTE		resetreq;
 	BYTE		trap;
-	BYTE		_dummy;
 
-	BYTE		cpl;
+	BYTE		page_wp;
+
+	BYTE		user_mode;
 	BYTE		protected_mode;
 	BYTE		paging;
 	BYTE		vm86;
@@ -228,7 +230,6 @@ extern I386CORE		i386core;
 #define	CPU_EXTMEMSIZE	i386core.e.extsize
 #define	CPU_INPADRS	i386core.e.inport
 
-extern BYTE 		iflags[];
 extern sigjmp_buf	exec_1step_jmpbuf;
 
 
@@ -242,7 +243,11 @@ extern sigjmp_buf	exec_1step_jmpbuf;
 
 /* version */
 #define	CPU_FAMILY	4
-#define	CPU_MODEL	2
+#if defined(USE_FPU)
+#define	CPU_MODEL	1	/* 486DX */
+#else
+#define	CPU_MODEL	2	/* 486SX */
+#endif
 #define	CPU_STEPPING	3
 
 /* feature */
@@ -339,6 +344,7 @@ do { \
 #define	CPU_EDI		CPU_REGS_DWORD(CPU_EDI_INDEX)
 #define CPU_EIP		CPU_STATSAVE.cpu_regs.eip.d
 #define CPU_PREV_EIP	CPU_STATSAVE.cpu_regs.prev_eip.d
+#define CPU_PREV_ESP	CPU_STATSAVE.cpu_regs.prev_esp.d
 
 #define	CPU_ES		CPU_REGS_SREG(CPU_ES_INDEX)
 #define	CPU_CS		CPU_REGS_SREG(CPU_CS_INDEX)
@@ -359,7 +365,9 @@ do { \
 #define CPU_FLAGL	CPU_STATSAVE.cpu_regs.eflags.b.l
 #define CPU_FLAGH	CPU_STATSAVE.cpu_regs.eflags.b.h
 #define CPU_TRAP	CPU_STATSAVE.cpu_stat.trap
-// #define CPU_INPORT	CPU_STATSAVE.cpu_stat.inport
+#if 0
+#define CPU_INPORT	CPU_STATSAVE.cpu_stat.inport
+#endif
 #define CPU_OV		CPU_STATSAVE.cpu_stat.ovflag
 
 #define C_FLAG		(1 << 0)
@@ -411,7 +419,9 @@ void set_eflags(DWORD new_flags, DWORD m
 #define	CPU_STAT_PM		CPU_STATSAVE.cpu_stat.protected_mode
 #define	CPU_STAT_VM86		CPU_STATSAVE.cpu_stat.vm86
 #define	CPU_STAT_PAGING		CPU_STATSAVE.cpu_stat.paging
-#define	CPU_STAT_CPL		CPU_STATSAVE.cpu_stat.cpl
+#define	CPU_STAT_WP		CPU_STATSAVE.cpu_stat.page_wp
+#define	CPU_STAT_CPL		CPU_STAT_SREG(CPU_CS_INDEX).rpl
+#define	CPU_STAT_USER_MODE	CPU_STATSAVE.cpu_stat.user_mode
 #define	CPU_STAT_PDE_BASE	CPU_STATSAVE.cpu_stat.pde_base
 
 #define	CPU_STAT_IOPL		((CPU_EFLAG & IOPL_FLAG) >> 12)
@@ -426,6 +436,15 @@ void set_eflags(DWORD new_flags, DWORD m
 #define	CPU_STAT_NERROR		CPU_STATSAVE.cpu_stat.nerror
 #define	CPU_STAT_PREV_EXCEPTION	CPU_STATSAVE.cpu_stat.prev_exception
 
+#define	CPU_MODE_SUPERVISER	0
+#define	CPU_MODE_USER		1
+#define	CPU_SET_CPL(cpl) \
+do { \
+	BYTE __t = (cpl) & 3; \
+	CPU_STAT_CPL = __t; \
+	CPU_STAT_USER_MODE = (__t == 3) ? CPU_MODE_USER : CPU_MODE_SUPERVISER; \
+} while (/*CONSTCOND*/ 0)
+
 #define CPU_CLI		do { CPU_FLAG &= ~I_FLAG;	\
 					CPU_TRAP = 0; } while (/*CONSTCOND*/ 0)
 #define CPU_STI		do { CPU_FLAG |= I_FLAG;	\
@@ -436,15 +455,15 @@ void set_eflags(DWORD new_flags, DWORD m
 #define CPU_IDTR_LIMIT	CPU_STATSAVE.cpu_sysregs.idtr_limit
 #define CPU_IDTR_BASE	CPU_STATSAVE.cpu_sysregs.idtr_base
 #define CPU_LDTR	CPU_STATSAVE.cpu_sysregs.ldtr
-#define CPU_LDTR_DESC	CPU_STATSAVE.cpu_sysregs.ldtr_desc
-#define CPU_LDTR_BASE	CPU_STATSAVE.cpu_sysregs.ldtr_desc.u.seg.segbase
-#define CPU_LDTR_END	CPU_STATSAVE.cpu_sysregs.ldtr_desc.u.seg.segend
-#define CPU_LDTR_LIMIT	CPU_STATSAVE.cpu_sysregs.ldtr_desc.u.seg.limit
+#define CPU_LDTR_DESC	CPU_STATSAVE.cpu_stat.ldtr_desc
+#define CPU_LDTR_BASE	CPU_STATSAVE.cpu_stat.ldtr_desc.u.seg.segbase
+#define CPU_LDTR_END	CPU_STATSAVE.cpu_stat.ldtr_desc.u.seg.segend
+#define CPU_LDTR_LIMIT	CPU_STATSAVE.cpu_stat.ldtr_desc.u.seg.limit
 #define CPU_TR		CPU_STATSAVE.cpu_sysregs.tr
-#define CPU_TR_DESC	CPU_STATSAVE.cpu_sysregs.tr_desc
-#define CPU_TR_BASE	CPU_STATSAVE.cpu_sysregs.tr_desc.u.seg.segbase
-#define CPU_TR_END	CPU_STATSAVE.cpu_sysregs.tr_desc.u.seg.segend
-#define CPU_TR_LIMIT	CPU_STATSAVE.cpu_sysregs.tr_desc.u.seg.limit
+#define CPU_TR_DESC	CPU_STATSAVE.cpu_stat.tr_desc
+#define CPU_TR_BASE	CPU_STATSAVE.cpu_stat.tr_desc.u.seg.segbase
+#define CPU_TR_END	CPU_STATSAVE.cpu_stat.tr_desc.u.seg.segend
+#define CPU_TR_LIMIT	CPU_STATSAVE.cpu_stat.tr_desc.u.seg.limit
 
 /*
  * control register
@@ -489,6 +508,8 @@ void set_eflags(DWORD new_flags, DWORD m
 
 
 void ia32_init(void);
+void ia32_initreg(void);
+void ia32_setextsize(UINT32 size);
 
 void ia32reset(void);
 void ia32shut(void);
@@ -505,8 +526,6 @@ void exec_1step(void);
 #define	INST_STRING	(1 << 1)
 #define	REP_CHECKZF	(1 << 7)
 
-void disasm(WORD cs, DWORD maddr);
-
 void ia32_printf(const char *buf, ...);
 void ia32_warning(const char *buf, ...);
 void ia32_panic(const char *buf, ...);
@@ -515,8 +534,10 @@ void ia32_bioscall(void);
 
 void FASTCALL change_pm(BOOL onoff);
 void FASTCALL change_vm(BOOL onoff);
+void FASTCALL change_pg(BOOL onoff);
 
-extern BYTE szpcflag[0x200];
+extern const UINT8 iflags[];
+#define	szpcflag	iflags
 extern BYTE szpflag_w[0x10000];
 
 extern BYTE  *reg8_b20[0x100];
@@ -530,6 +551,13 @@ extern const char *reg8_str[8];
 extern const char *reg16_str[8];
 extern const char *reg32_str[8];
 
+char *cpu_reg2str(void);
+#if defined(USE_FPU)
+char *fpu_reg2str(void);
+#endif
+void dbg_printf(const char *str, ...);
+
+
 /*
  * Misc.
  */