--- np2/i386c/ia32/cpu.h	2004/02/20 16:09:04	1.19
+++ np2/i386c/ia32/cpu.h	2004/03/08 12:56:22	1.22
@@ -1,4 +1,4 @@
-/*	$Id: cpu.h,v 1.19 2004/02/20 16:09:04 monaka Exp $	*/
+/*	$Id: cpu.h,v 1.22 2004/03/08 12:56:22 monaka Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -109,13 +109,18 @@ enum {
 };
 
 enum {
-	CPU_DEBUG_REG_NUM = 8
+	CPU_DEBUG_REG_NUM = 8,
+	CPU_DEBUG_REG_INDEX_NUM = 4
 };
 
 enum {
 	MAX_PREFIX = 8
 };
 
+enum {
+	CPU_PREFETCH_QUEUE_LENGTH = 16
+};
+
 typedef struct {
 	REG32		reg[CPU_REG_NUM];
 	UINT16		sreg[CPU_SEGREG_NUM];
@@ -152,6 +157,10 @@ typedef struct {
 	descriptor_t	ldtr;
 	descriptor_t	tr;
 
+	BYTE		prefetch[CPU_PREFETCH_QUEUE_LENGTH];
+	SINT8		prefetch_remain;
+	UINT8		pad2[2];
+
 	UINT32		adrsmask;
 	UINT32		ovflag;
 
@@ -167,7 +176,9 @@ typedef struct {
 	UINT8		user_mode;
 
 	UINT8		hlt;
-	UINT8		pad[3];
+	UINT8		bp;	/* break point bitmap */
+	UINT8		bp_ev;	/* break point event */
+	UINT8		pad;
 
 	UINT32		pde_base;
 
@@ -441,6 +452,15 @@ void set_eflags(UINT32 new_flags, UINT32
 #define	CPU_STAT_EXCEPTION_COUNTER_INC()	CPU_STATSAVE.cpu_stat.nerror++
 #define	CPU_STAT_EXCEPTION_COUNTER_CLEAR()	CPU_STATSAVE.cpu_stat.nerror = 0
 
+#define	CPU_PREFETCHQ		CPU_STATSAVE.cpu_stat.prefetch
+#define	CPU_PREFETCHQ_REMAIN	CPU_STATSAVE.cpu_stat.prefetch_remain
+
+#if defined(IA32_SUPPORT_PREFETCH_QUEUE)
+#define	CPU_PREFETCH_CLEAR()	CPU_PREFETCHQ_REMAIN = 0
+#else	/* !IA32_SUPPORT_PREFETCH_QUEUE */
+#define	CPU_PREFETCH_CLEAR()
+#endif	/* IA32_SUPPORT_PREFETCH_QUEUE */
+
 #define	CPU_MODE_SUPERVISER	0
 #define	CPU_MODE_USER		1
 #define	CPU_SET_CPL(cpl) \
@@ -518,6 +538,41 @@ do { \
 #define	CPU_CR4_OSFXSR		(1 << 9)
 #define	CPU_CR4_OSXMMEXCPT	(1 << 10)
 
+/*
+ * debug register
+ */
+#define	CPU_DR(r)		CPU_STATSAVE.cpu_regs.dr[(r)]
+#define	CPU_DR6			CPU_DR(6)
+#define	CPU_DR7			CPU_DR(7)
+
+#define	CPU_STAT_BP		CPU_STATSAVE.cpu_stat.bp
+#define	CPU_STAT_BP_EVENT	CPU_STATSAVE.cpu_stat.bp_ev
+#define	CPU_STAT_BP_EVENT_B(r)	(1 << (r))
+#define	CPU_STAT_BP_EVENT_DR	(1 << 4)	/* fault */
+#define	CPU_STAT_BP_EVENT_STEP	(1 << 5)	/* as CPU_TRAP */
+#define	CPU_STAT_BP_EVENT_TASK	(1 << 6)
+#define	CPU_STAT_BP_EVENT_RF	(1 << 7)	/* RF_FLAG */
+
+#define	CPU_DR6_B(r)		(1 << (r))
+#define	CPU_DR6_BD		(1 << 13)
+#define	CPU_DR6_BS		(1 << 14)
+#define	CPU_DR6_BT		(1 << 15)
+
+#define	CPU_DR7_L(r)		(1 << ((r) * 2))
+#define	CPU_DR7_G(r)		(1 << ((r) * 2 + 1))
+#define	CPU_DR7_LE		(1 << 8)
+#define	CPU_DR7_GE		(1 << 9)
+#define	CPU_DR7_GD		(1 << 13)
+#define	CPU_DR7_RW(r)		(3 << ((r) * 4 + 16))
+#define	CPU_DR7_LEN(r)		(3 << ((r) * 4 + 16 + 2))
+
+#define	CPU_DR7_GET_RW(r)	((CPU_DR7) >> (16 + (r) * 4))
+#define	CPU_DR7_RW_CODE		0
+#define	CPU_DR7_RW_RO		1
+#define	CPU_DR7_RW_IO		2
+#define	CPU_DR7_RW_RW		3
+
+#define	CPU_DR7_GET_LEN(r)	((CPU_DR7) >> (16 + 2 + (r) * 4))
 
 void ia32_init(void);
 void ia32_initreg(void);
@@ -526,9 +581,6 @@ void ia32_setextsize(UINT32 size);
 void ia32reset(void);
 void ia32shut(void);
 void ia32(void);
-void ia32withtrap(void);
-void ia32withdma(void);
-
 void ia32_step(void);
 void CPUCALL ia32_interrupt(int vect);
 void CPUCALL ia32_exception(int vect, int p1, int p2);
@@ -538,8 +590,6 @@ void exec_1step(void);
 #define	INST_STRING	(1 << 1)
 #define	REP_CHECKZF	(1 << 7)
 
-int disasm(UINT32 *eip, char *buf, size_t size);
-
 void ia32_printf(const char *buf, ...);
 void ia32_warning(const char *buf, ...);
 void ia32_panic(const char *buf, ...);
@@ -581,6 +631,43 @@ void idtr_dump(UINT32 base, UINT limit);
 void ldtr_dump(UINT32 base, UINT limit);
 void tr_dump(UINT16 selector, UINT32 base, UINT limit);
 
+/*
+ * disasm
+ */
+/* context */
+typedef struct {
+	UINT32 val;
+
+	UINT32 eip;
+	BOOL op32;
+	BOOL as32;
+
+	UINT32 baseaddr;
+	UINT8 opcode[3];
+	UINT8 modrm;
+	UINT8 sib;
+
+	BOOL useseg;
+	int seg;
+
+	UINT8 opbyte[32];
+	int nopbytes;
+
+	char str[256];
+	size_t remain;
+
+	char *next;
+	char *prefix;
+	char *op;
+	char *arg[3];
+	int narg;
+
+	char pad;
+} disasm_context_t;
+
+int disasm(UINT32 *eip, disasm_context_t *ctx);
+
+
 #ifdef __cplusplus
 }
 #endif