--- np2/i386c/ia32/cpu.h	2004/03/08 12:56:22	1.22
+++ np2/i386c/ia32/cpu.h	2011/12/21 16:33:44	1.39
@@ -1,5 +1,3 @@
-/*	$Id: cpu.h,v 1.22 2004/03/08 12:56:22 monaka Exp $	*/
-
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
  * All rights reserved.
@@ -12,8 +10,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -71,6 +67,10 @@ typedef union {
 	UINT32	d;
 } REG32;
 
+typedef struct {
+	UINT8	b[10];
+} REG80;
+
 #ifdef __cplusplus
 }
 #endif
@@ -117,10 +117,6 @@ enum {
 	MAX_PREFIX = 8
 };
 
-enum {
-	CPU_PREFETCH_QUEUE_LENGTH = 16
-};
-
 typedef struct {
 	REG32		reg[CPU_REG_NUM];
 	UINT16		sreg[CPU_SEGREG_NUM];
@@ -137,8 +133,10 @@ typedef struct {
 
 typedef struct {
 	UINT16		gdtr_limit;
+	UINT16		pad0;
 	UINT32		gdtr_base;
 	UINT16		idtr_limit;
+	UINT16		pad1;
 	UINT32		idtr_base;
 
 	UINT16		ldtr;
@@ -157,10 +155,6 @@ typedef struct {
 	descriptor_t	ldtr;
 	descriptor_t	tr;
 
-	BYTE		prefetch[CPU_PREFETCH_QUEUE_LENGTH];
-	SINT8		prefetch_remain;
-	UINT8		pad2[2];
-
 	UINT32		adrsmask;
 	UINT32		ovflag;
 
@@ -178,7 +172,8 @@ typedef struct {
 	UINT8		hlt;
 	UINT8		bp;	/* break point bitmap */
 	UINT8		bp_ev;	/* break point event */
-	UINT8		pad;
+
+	UINT8		backout_sp;	/* backout ESP, when exception */
 
 	UINT32		pde_base;
 
@@ -197,6 +192,46 @@ typedef struct {
 	UINT32		seg_base;
 } CPU_INST;
 
+/* FPU */
+enum {
+	FPU_REG_NUM = 8
+};
+
+typedef struct {
+	UINT16		seg;
+	UINT16		pad;
+	UINT32		offset;
+} FPU_PTR;
+
+typedef struct {
+	UINT16		control;
+	UINT16		status;
+	UINT16		op;
+
+	FPU_PTR		inst;
+	FPU_PTR		data;
+} FPU_REGS;
+
+typedef struct {
+	UINT8		valid;	/* レジスタ有効 */
+	UINT8		sign;	/* 符号 */
+	UINT8		zero;	/* ゼロ */
+	UINT8		inf;	/* ∞ */
+	UINT8		nan;	/* NaN */
+	UINT8		denorm;	/* 非正規化 */
+	SINT16		exp;	/* 指数部 */
+	UINT64		num;	/* 小数部 */
+} FP_REG;
+
+typedef struct {
+	UINT8		top;	/* スタック位置 */
+	UINT8		pc;	/* 精度 */
+	UINT8		rc;	/* 丸め */
+	UINT8		dmy[1];
+
+	FP_REG		reg[FPU_REG_NUM];
+} FPU_STAT;
+
 typedef struct {
 	CPU_REGS	cpu_regs;
 	CPU_SYSREGS	cpu_sysregs;
@@ -204,6 +239,11 @@ typedef struct {
 	CPU_INST	cpu_inst;
 	CPU_INST	cpu_inst_default;
 
+#if defined(USE_FPU)
+	FPU_REGS	fpu_regs;
+	FPU_STAT	fpu_stat;
+#endif
+
 	/* protected by cpu shut */
 	UINT8		cpu_type;
 	UINT8		itfbank;
@@ -213,10 +253,14 @@ typedef struct {
 	UINT32		clock;
 } I386STAT;
 
-typedef struct {					/* for ver0.73 */
-	BYTE		*ext;
+typedef struct {
+	UINT8		*ext;
 	UINT32		extsize;
+	UINT8		*extbase;	/* = ext - 0x100000 */
+	UINT32		extlimit16mb;	/* = extsize + 0x100000 (MAX:16MB) */
+	UINT32		extlimit4gb;	/* = extsize + 0x100000 */
 	UINT32		inport;
+	UINT8		*ems[4];
 } I386EXT;
 
 typedef struct {
@@ -242,7 +286,11 @@ extern I386CORE		i386core;
 
 #define	CPU_EXTMEM	i386core.e.ext
 #define	CPU_EXTMEMSIZE	i386core.e.extsize
+#define	CPU_EXTMEMBASE	i386core.e.extbase
+#define	CPU_EXTLIMIT16	i386core.e.extlimit16mb
+#define	CPU_EXTLIMIT	i386core.e.extlimit4gb
 #define	CPU_INPADRS	i386core.e.inport
+#define	CPU_EMSPTR	i386core.e.ems
 
 extern sigjmp_buf	exec_1step_jmpbuf;
 
@@ -297,7 +345,7 @@ extern sigjmp_buf	exec_1step_jmpbuf;
 /*				(1 << 29) */
 /*				(1 << 30) */
 /*				(1 << 31) */
-#ifdef USE_FPU
+#if defined(USE_FPU)
 #define	CPU_FEATURES		(CPU_FEATURE_CMOV|CPU_FEATURE_FPU)
 #else
 #define	CPU_FEATURES		(CPU_FEATURE_CMOV)
@@ -311,22 +359,8 @@ extern sigjmp_buf	exec_1step_jmpbuf;
 #define	CPU_REGS_SREG(n)	CPU_STATSAVE.cpu_regs.sreg[(n)]
 
 #define	CPU_STAT_SREG(n)	CPU_STATSAVE.cpu_stat.sreg[(n)]
-#define	CPU_STAT_SREGBASE(n)	CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.segbase
-#define	CPU_STAT_SREGEND(n)	CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.segend
-#define	CPU_STAT_SREGLIMIT(n)	CPU_STATSAVE.cpu_stat.sreg[(n)].u.seg.limit
-#define	CPU_STAT_SREG_CLEAR(n) \
-do { \
-	memset(&CPU_STAT_SREG(n), 0, sizeof(descriptor_t)); \
-} while (/*CONSTCOND*/ 0)
-#define	CPU_STAT_SREG_INIT(n) \
-do { \
-	descriptor_t sd; \
-\
-	memset(&sd, 0, sizeof(sd)); \
-	sd.u.seg.limit = 0xffff; \
-	CPU_SET_SEGDESC_DEFAULT(&sd, (n), 0); \
-	CPU_STAT_SREG(n) = sd; \
-} while (/*CONSTCOND*/ 0)
+#define	CPU_STAT_SREGBASE(n)	CPU_STAT_SREG((n)).u.seg.segbase
+#define	CPU_STAT_SREGLIMIT(n)	CPU_STAT_SREG((n)).u.seg.limit
 
 
 #define CPU_AL		CPU_REGS_BYTEL(CPU_EAX_INDEX)
@@ -367,6 +401,13 @@ do { \
 #define	CPU_FS		CPU_REGS_SREG(CPU_FS_INDEX)
 #define	CPU_GS		CPU_REGS_SREG(CPU_GS_INDEX)
 
+#define	CPU_ES_DESC	CPU_STAT_SREG(CPU_ES_INDEX)
+#define	CPU_CS_DESC	CPU_STAT_SREG(CPU_CS_INDEX)
+#define	CPU_SS_DESC	CPU_STAT_SREG(CPU_SS_INDEX)
+#define	CPU_DS_DESC	CPU_STAT_SREG(CPU_DS_INDEX)
+#define	CPU_FS_DESC	CPU_STAT_SREG(CPU_FS_INDEX)
+#define	CPU_GS_DESC	CPU_STAT_SREG(CPU_GS_INDEX)
+
 #define ES_BASE		CPU_STAT_SREGBASE(CPU_ES_INDEX)
 #define CS_BASE		CPU_STAT_SREGBASE(CPU_CS_INDEX)
 #define SS_BASE		CPU_STAT_SREGBASE(CPU_SS_INDEX)
@@ -406,11 +447,11 @@ do { \
 #define	ALL_FLAG	(SZAPC_FLAG|T_FLAG|I_FLAG|D_FLAG|O_FLAG|IOPL_FLAG|NT_FLAG)
 #define	ALL_EFLAG	(ALL_FLAG|RF_FLAG|VM_FLAG|AC_FLAG|VIF_FLAG|VIP_FLAG|ID_FLAG)
 
-#define	REAL_FLAGREG	((CPU_FLAG & 0xf7ff) | (CPU_OV ? O_FLAG : 0))
-#define	REAL_EFLAGREG	((CPU_EFLAG & 0xfffff7ff) | (CPU_OV ? O_FLAG : 0))
+#define	REAL_FLAGREG	((CPU_FLAG & 0xf7ff) | (CPU_OV ? O_FLAG : 0) | 2)
+#define	REAL_EFLAGREG	((CPU_EFLAG & 0xfffff7ff) | (CPU_OV ? O_FLAG : 0) | 2)
 
-void set_flags(UINT16 new_flags, UINT16 mask);
-void set_eflags(UINT32 new_flags, UINT32 mask);
+void FASTCALL set_flags(UINT16 new_flags, UINT16 mask);
+void FASTCALL set_eflags(UINT32 new_flags, UINT32 mask);
 
 
 #define	CPU_INST_OP32		CPU_STATSAVE.cpu_inst.op_32
@@ -423,7 +464,6 @@ void set_eflags(UINT32 new_flags, UINT32
 
 #define	CPU_STAT_CS_BASE	CPU_STAT_SREGBASE(CPU_CS_INDEX)
 #define	CPU_STAT_CS_LIMIT	CPU_STAT_SREGLIMIT(CPU_CS_INDEX)
-#define	CPU_STAT_CS_END		CPU_STAT_SREGEND(CPU_CS_INDEX)
 
 #define	CPU_STAT_ADRSMASK	CPU_STATSAVE.cpu_stat.adrsmask
 #define	CPU_STAT_SS32		CPU_STATSAVE.cpu_stat.ss_32
@@ -432,9 +472,19 @@ void set_eflags(UINT32 new_flags, UINT32
 #define	CPU_STAT_PAGING		CPU_STATSAVE.cpu_stat.paging
 #define	CPU_STAT_VM86		CPU_STATSAVE.cpu_stat.vm86
 #define	CPU_STAT_WP		CPU_STATSAVE.cpu_stat.page_wp
-#define	CPU_STAT_CPL		CPU_STAT_SREG(CPU_CS_INDEX).rpl
+#define	CPU_STAT_CPL		CPU_CS_DESC.rpl
 #define	CPU_STAT_USER_MODE	CPU_STATSAVE.cpu_stat.user_mode
 #define	CPU_STAT_PDE_BASE	CPU_STATSAVE.cpu_stat.pde_base
+#define	CPU_SET_PREV_ESP1(esp) \
+do { \
+	CPU_STATSAVE.cpu_stat.backout_sp = 1; \
+	CPU_PREV_ESP = (esp); \
+} while (/*CONSTCOND*/0)
+#define	CPU_SET_PREV_ESP()	CPU_SET_PREV_ESP1(CPU_ESP)
+#define	CPU_CLEAR_PREV_ESP() \
+do { \
+	CPU_STATSAVE.cpu_stat.backout_sp = 0; \
+} while (/*CONSTCOND*/0)
 
 #define	CPU_STAT_HLT		CPU_STATSAVE.cpu_stat.hlt
 
@@ -452,23 +502,8 @@ void set_eflags(UINT32 new_flags, UINT32
 #define	CPU_STAT_EXCEPTION_COUNTER_INC()	CPU_STATSAVE.cpu_stat.nerror++
 #define	CPU_STAT_EXCEPTION_COUNTER_CLEAR()	CPU_STATSAVE.cpu_stat.nerror = 0
 
-#define	CPU_PREFETCHQ		CPU_STATSAVE.cpu_stat.prefetch
-#define	CPU_PREFETCHQ_REMAIN	CPU_STATSAVE.cpu_stat.prefetch_remain
-
-#if defined(IA32_SUPPORT_PREFETCH_QUEUE)
-#define	CPU_PREFETCH_CLEAR()	CPU_PREFETCHQ_REMAIN = 0
-#else	/* !IA32_SUPPORT_PREFETCH_QUEUE */
-#define	CPU_PREFETCH_CLEAR()
-#endif	/* IA32_SUPPORT_PREFETCH_QUEUE */
-
 #define	CPU_MODE_SUPERVISER	0
-#define	CPU_MODE_USER		1
-#define	CPU_SET_CPL(cpl) \
-do { \
-	UINT8 __t = (UINT8)((cpl) & 3); \
-	CPU_STAT_CPL = __t; \
-	CPU_STAT_USER_MODE = (__t == 3) ? CPU_MODE_USER : CPU_MODE_SUPERVISER; \
-} while (/*CONSTCOND*/ 0)
+#define	CPU_MODE_USER		(1 << 3)
 
 #define CPU_CLI \
 do { \
@@ -479,7 +514,7 @@ do { \
 #define CPU_STI \
 do { \
 	CPU_FLAG |= I_FLAG; \
-	CPU_TRAP = (CPU_FLAG >> 8) & 1; \
+	CPU_TRAP = (CPU_FLAG & (I_FLAG|T_FLAG)) == (I_FLAG|T_FLAG) ; \
 } while (/*CONSTCOND*/0)
 
 #define CPU_GDTR_LIMIT	CPU_STATSAVE.cpu_sysregs.gdtr_limit
@@ -488,14 +523,12 @@ do { \
 #define CPU_IDTR_BASE	CPU_STATSAVE.cpu_sysregs.idtr_base
 #define CPU_LDTR	CPU_STATSAVE.cpu_sysregs.ldtr
 #define CPU_LDTR_DESC	CPU_STATSAVE.cpu_stat.ldtr
-#define CPU_LDTR_BASE	CPU_STATSAVE.cpu_stat.ldtr.u.seg.segbase
-#define CPU_LDTR_END	CPU_STATSAVE.cpu_stat.ldtr.u.seg.segend
-#define CPU_LDTR_LIMIT	CPU_STATSAVE.cpu_stat.ldtr.u.seg.limit
+#define CPU_LDTR_BASE	CPU_LDTR_DESC.u.seg.segbase
+#define CPU_LDTR_LIMIT	CPU_LDTR_DESC.u.seg.limit
 #define CPU_TR		CPU_STATSAVE.cpu_sysregs.tr
 #define CPU_TR_DESC	CPU_STATSAVE.cpu_stat.tr
-#define CPU_TR_BASE	CPU_STATSAVE.cpu_stat.tr.u.seg.segbase
-#define CPU_TR_END	CPU_STATSAVE.cpu_stat.tr.u.seg.segend
-#define CPU_TR_LIMIT	CPU_STATSAVE.cpu_stat.tr.u.seg.limit
+#define CPU_TR_BASE	CPU_TR_DESC.u.seg.segbase
+#define CPU_TR_LIMIT	CPU_TR_DESC.u.seg.limit
 
 /*
  * control register
@@ -520,6 +553,7 @@ do { \
 #define	CPU_CR0_NW		(1 << 29)
 #define	CPU_CR0_CD		(1 << 30)
 #define	CPU_CR0_PG		(1 << 31)
+#define	CPU_CR0_ALL		(CPU_CR0_PE|CPU_CR0_MP|CPU_CR0_EM|CPU_CR0_TS|CPU_CR0_ET|CPU_CR0_NE|CPU_CR0_WP|CPU_CR0_AM|CPU_CR0_NW|CPU_CR0_CD|CPU_CR0_PG)
 
 #define	CPU_CR3_PD_MASK		0xfffff000
 #define	CPU_CR3_PWT		(1 << 3)
@@ -577,12 +611,14 @@ do { \
 void ia32_init(void);
 void ia32_initreg(void);
 void ia32_setextsize(UINT32 size);
+void ia32_setemm(UINT frame, UINT32 addr);
 
 void ia32reset(void);
 void ia32shut(void);
+void ia32a20enable(BOOL enable);
 void ia32(void);
 void ia32_step(void);
-void CPUCALL ia32_interrupt(int vect);
+void CPUCALL ia32_interrupt(int vect, int soft);
 void CPUCALL ia32_exception(int vect, int p1, int p2);
 
 void exec_1step(void);
@@ -600,6 +636,9 @@ void FASTCALL change_pm(BOOL onoff);
 void FASTCALL change_vm(BOOL onoff);
 void FASTCALL change_pg(BOOL onoff);
 
+void FASTCALL set_cr3(UINT32 new_cr3);
+void FASTCALL set_cpl(int new_cpl);
+
 extern const UINT8 iflags[];
 #define	szpcflag	iflags
 extern UINT8 szpflag_w[0x10000];
@@ -624,12 +663,82 @@ void dbg_printf(const char *str, ...);
 
 
 /*
+ * FPU
+ */
+#define	FPU_REGS		CPU_STATSAVE.fpu_regs
+#define	FPU_CTRLWORD		FPU_REGS.control
+#define	FPU_STATUSWORD		FPU_REGS.status
+#define	FPU_INSTPTR		FPU_REGS.inst
+#define	FPU_DATAPTR		FPU_REGS.data
+#define	FPU_LASTINSTOP		FPU_REGS.op
+#define	FPU_INSTPTR_OFFSET	FPU_REGS.inst.offset
+#define	FPU_INSTPTR_SEG		FPU_REGS.inst.seg
+#define	FPU_DATAPTR_OFFSET	FPU_REGS.data.offset
+#define	FPU_DATAPTR_SEG		FPU_REGS.data.seg
+
+#define	FPU_STAT		CPU_STATSAVE.fpu_stat
+#define	FPU_STAT_TOP		FPU_STAT.top
+#define	FPU_STAT_PC		FPU_STAT.pc
+#define	FPU_STAT_RC		FPU_STAT.rc
+
+#define	FPU_ST(i)		FPU_STAT.reg[((i) + FPU_STAT_TOP) & 7]
+#define	FPU_REG(i)		FPU_STAT.reg[i]
+
+/* FPU status register */
+#define	FP_IE_FLAG	(1 << 0)	/* 無効な動作 */
+#define	FP_DE_FLAG	(1 << 1)	/* デノーマライズド・オペランド */
+#define	FP_ZE_FLAG	(1 << 2)	/* ゼロによる除算 */
+#define	FP_OE_FLAG	(1 << 3)	/* オーバーフロー */
+#define	FP_UE_FLAG	(1 << 4)	/* アンダーフロー */
+#define	FP_PE_FLAG	(1 << 5)	/* 精度 */
+#define	FP_SF_FLAG	(1 << 6)	/* スタックフォルト */
+#define	FP_ES_FLAG	(1 << 7)	/* エラーサマリステータス */
+#define	FP_C0_FLAG	(1 << 8)	/* 条件コード */
+#define	FP_C1_FLAG	(1 << 9)	/* 条件コード */
+#define	FP_C2_FLAG	(1 << 10)	/* 条件コード */
+#define	FP_TOP_FLAG	(7 << 11)	/* スタックポイントのトップ */
+#define	FP_C3_FLAG	(1 << 14)	/* 条件コード */
+#define	FP_B_FLAG	(1 << 15)	/* FPU ビジー */
+
+#define	FP_TOP_SHIFT	11
+#define	FP_TOP_GET()	((FPU_STATUSWORD & FP_TOP_FLAG) >> FP_TOP_SHIFT)
+#define	FP_TOP_SET(v)	((FPU_STATUSWORD & ~FP_TOP_FLAG) | ((v) << FP_TOP_SHIFT))
+
+#define	FPU_STAT_TOP_INC() \
+do { \
+	FPU_STAT.top = (FPU_STAT.top + 1) & 7; \
+} while (/*CONSTCOND*/0)
+#define	FPU_STAT_TOP_DEC() \
+do { \
+	FPU_STAT.top = (FPU_STAT.top - 1) & 7; \
+} while (/*CONSTCOND*/0)
+
+/* FPU control register */
+#define	FP_CTRL_PC_SHIFT	8	/* 精度制御 */
+#define	FP_CTRL_RC_SHIFT	10	/* 丸め制御 */
+
+#define	FP_CTRL_PC_24		0	/* 単精度 */
+#define	FP_CTRL_PC_53		1	/* 倍精度 */
+#define	FP_CTRL_PC_64		3	/* 拡張精度 */
+
+#define	FP_CTRL_RC_NEAREST_EVEN	0
+#define	FP_CTRL_RC_DOWN		1
+#define	FP_CTRL_RC_UP		2
+#define	FP_CTRL_RC_TO_ZERO	3
+
+
+/*
  * Misc.
  */
+void memory_dump(int idx, UINT32 madr);
 void gdtr_dump(UINT32 base, UINT limit);
 void idtr_dump(UINT32 base, UINT limit);
 void ldtr_dump(UINT32 base, UINT limit);
 void tr_dump(UINT16 selector, UINT32 base, UINT limit);
+UINT32 pde_dump(UINT32 base, int idx);
+void segdesc_dump(descriptor_t *sdp);
+UINT32 convert_laddr_to_paddr(UINT32 laddr);
+UINT32 convert_vaddr_to_paddr(unsigned int idx, UINT32 offset);
 
 /*
  * disasm
@@ -667,7 +776,6 @@ typedef struct {
 
 int disasm(UINT32 *eip, disasm_context_t *ctx);
 
-
 #ifdef __cplusplus
 }
 #endif