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| version 1.7, 2005/03/12 12:32:54 | version 1.11, 2011/12/21 18:02:47 |
|---|---|
| Line 1 | Line 1 |
| /* $Id$ */ | |
| /* | /* |
| * Copyright (c) 2003 NONAKA Kimihiro | * Copyright (c) 2003 NONAKA Kimihiro |
| * All rights reserved. | * All rights reserved. |
| Line 32 | Line 30 |
| #include "iocore.h" | #include "iocore.h" |
| #include "memory.h" | #include "memory.h" |
| static void IOOUTCALL check_io(UINT port, UINT len) GCC_ATTR_REGPARM; | static void CPUCALL check_io(UINT port, UINT len); |
| static void IOOUTCALL | static void CPUCALL |
| check_io(UINT port, UINT len) | check_io(UINT port, UINT len) |
| { | { |
| UINT off; | UINT off; |
| Line 64 check_io(UINT port, UINT len) | Line 62 check_io(UINT port, UINT len) |
| } | } |
| } | } |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) && CPU_FAMILY >= 5 | UINT8 IOINPCALL |
| INLINE static void IOOUTCALL | |
| check_ioport_break_point(UINT port, UINT length) | |
| { | |
| int i; | |
| if (CPU_STAT_BP && !(CPU_EFLAG & RF_FLAG)) { | |
| for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | |
| if ((CPU_STAT_BP & (1 << i)) | |
| && (CPU_DR7_GET_RW(i) == CPU_DR7_RW_IO) | |
| && ((port <= CPU_DR(i) && port + length > CPU_DR(i)) | |
| || (port > CPU_DR(i) && port <= CPU_DR(i) + CPU_DR7_GET_LEN(i)))) { | |
| CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_B(i); | |
| } | |
| } | |
| } | |
| } | |
| #else | |
| #define check_ioport_break_point(port, length) | |
| #endif | |
| UINT8 | |
| cpu_in(UINT port) | cpu_in(UINT port) |
| { | { |
| if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { |
| check_io(port, 1); | check_io(port, 1); |
| } | } |
| check_ioport_break_point(port, 1); | |
| return iocore_inp8(port); | return iocore_inp8(port); |
| } | } |
| UINT16 | UINT16 IOINPCALL |
| cpu_in_w(UINT port) | cpu_in_w(UINT port) |
| { | { |
| if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { |
| check_io(port, 2); | check_io(port, 2); |
| } | } |
| check_ioport_break_point(port, 2); | |
| return iocore_inp16(port); | return iocore_inp16(port); |
| } | } |
| UINT32 | UINT32 IOINPCALL |
| cpu_in_d(UINT port) | cpu_in_d(UINT port) |
| { | { |
| if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { |
| check_io(port, 4); | check_io(port, 4); |
| } | } |
| check_ioport_break_point(port, 4); | |
| return iocore_inp32(port); | return iocore_inp32(port); |
| } | } |
| void | void IOOUTCALL |
| cpu_out(UINT port, UINT8 data) | cpu_out(UINT port, UINT8 data) |
| { | { |
| if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { |
| check_io(port, 1); | check_io(port, 1); |
| } | } |
| check_ioport_break_point(port, 1); | |
| iocore_out8(port, data); | iocore_out8(port, data); |
| } | } |
| void | void IOOUTCALL |
| cpu_out_w(UINT port, UINT16 data) | cpu_out_w(UINT port, UINT16 data) |
| { | { |
| if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { |
| check_io(port, 2); | check_io(port, 2); |
| } | } |
| check_ioport_break_point(port, 2); | |
| iocore_out16(port, data); | iocore_out16(port, data); |
| } | } |
| void | void IOOUTCALL |
| cpu_out_d(UINT port, UINT32 data) | cpu_out_d(UINT port, UINT32 data) |
| { | { |
| if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { |
| check_io(port, 4); | check_io(port, 4); |
| } | } |
| check_ioport_break_point(port, 4); | |
| iocore_out32(port, data); | iocore_out32(port, data); |
| } | } |