| version 1.3, 2004/02/05 16:43:44 | version 1.5, 2004/03/08 12:56:22 | 
| Line 34 | Line 34 | 
 |  |  | 
 |  |  | 
 | static void | static void | 
| check_io(WORD port, DWORD len) | check_io(UINT port, UINT len) | 
 | { | { | 
| WORD off; | UINT off; | 
| BYTE bit; | UINT8 bit; | 
| BYTE map; | UINT8 map; | 
 |  |  | 
 | if (CPU_STAT_IOLIMIT == 0) { | if (CPU_STAT_IOLIMIT == 0) { | 
 | VERBOSE(("check_io: CPU_STAT_IOLIMIT == 0 (port = %04x, len = %d)", port, len)); | VERBOSE(("check_io: CPU_STAT_IOLIMIT == 0 (port = %04x, len = %d)", port, len)); | 
| Line 63  check_io(WORD port, DWORD len) | Line 63  check_io(WORD port, DWORD len) | 
 | } | } | 
 | } | } | 
 |  |  | 
| BYTE | #if defined(IA32_SUPPORT_DEBUG_REGISTER) && CPU_FAMILY >= 5 | 
| cpu_in(WORD port) | INLINE static void | 
|  | check_ioport_break_point(UINT port, UINT length) | 
|  | { | 
|  | int i; | 
|  |  | 
|  | if (CPU_STAT_BP && !(CPU_EFLAG & RF_FLAG)) { | 
|  | for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | 
|  | if ((CPU_STAT_BP & (1 << i)) | 
|  | && (CPU_DR7_GET_RW(i) == CPU_DR7_RW_IO) | 
|  |  | 
|  | && ((port <= CPU_DR(i) && port + length > CPU_DR(i)) | 
|  | || (port > CPU_DR(i) && port <= CPU_DR(i) + CPU_DR7_GET_LEN(i)))) { | 
|  | CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_B(i); | 
|  | } | 
|  | } | 
|  | } | 
|  | } | 
|  | #else | 
|  | #define check_ioport_break_point(port, length) | 
|  | #endif | 
|  |  | 
|  | UINT8 | 
|  | cpu_in(UINT port) | 
 | { | { | 
 |  |  | 
 | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | 
 | check_io(port, 1); | check_io(port, 1); | 
 | } | } | 
 |  | check_ioport_break_point(port, 1); | 
 | return iocore_inp8(port); | return iocore_inp8(port); | 
 | } | } | 
 |  |  | 
| WORD | UINT16 | 
| cpu_in_w(WORD port) | cpu_in_w(UINT port) | 
 | { | { | 
 |  |  | 
 | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | 
 | check_io(port, 2); | check_io(port, 2); | 
 | } | } | 
 |  | check_ioport_break_point(port, 2); | 
 | return iocore_inp16(port); | return iocore_inp16(port); | 
 | } | } | 
 |  |  | 
| DWORD | UINT32 | 
| cpu_in_d(WORD port) | cpu_in_d(UINT port) | 
 | { | { | 
 |  |  | 
 | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | 
 | check_io(port, 4); | check_io(port, 4); | 
 | } | } | 
 |  | check_ioport_break_point(port, 4); | 
 | return iocore_inp32(port); | return iocore_inp32(port); | 
 | } | } | 
 |  |  | 
 | void | void | 
| cpu_out(WORD port, BYTE data) | cpu_out(UINT port, UINT8 data) | 
 | { | { | 
 |  |  | 
 | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | 
 | check_io(port, 1); | check_io(port, 1); | 
 | } | } | 
 |  | check_ioport_break_point(port, 1); | 
 | iocore_out8(port, data); | iocore_out8(port, data); | 
 | } | } | 
 |  |  | 
 | void | void | 
| cpu_out_w(WORD port, WORD data) | cpu_out_w(UINT port, UINT16 data) | 
 | { | { | 
 |  |  | 
 | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | 
 | check_io(port, 2); | check_io(port, 2); | 
 | } | } | 
 |  | check_ioport_break_point(port, 2); | 
 | iocore_out16(port, data); | iocore_out16(port, data); | 
 | } | } | 
 |  |  | 
 | void | void | 
| cpu_out_d(WORD port, DWORD data) | cpu_out_d(UINT port, UINT32 data) | 
 | { | { | 
 |  |  | 
 | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) { | 
 | check_io(port, 4); | check_io(port, 4); | 
 | } | } | 
 |  | check_ioport_break_point(port, 4); | 
 | iocore_out32(port, data); | iocore_out32(port, data); | 
 | } | } |